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Remote I/O module 16 DI
AL4043
53
11.1.1.5 Block Configuration (400 - 408)
Register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
400
X08:
DI2
INV
X08:
DI1
INV
X07:
DI2
INV
X07:
DI1
INV
X06:
DI2
INV
X06:
DI1
INV
X05:
DI2
INV
X05:
DI1
INV
X04:
DI2
INV
X04:
DI1
INV
X03:
DI2
INV
X03:
DI1
INV
X02:
DI2
INV
X02:
DI1
INV
X01:
DI2
INV
X01:
DI1
INV
401
X08:
DI2
HL
X08:
DI1
HL
X07:
DI2
HL
X07:
DI1
HL
X06:
DI2
HL
X06:
DI1
HL
X05:
DI2
HL
X05:
DI1
HL
X04:
DI2
HL
X04:
DI1
HL
X03:
DI2
HL
X03:
DI1
HL
X02:
DI2
HL
X02:
DI1
HL
X01:
DI2
HL
X01:
DI1
HL
402
reserved
X08:
DIS
X07:
DIS
X06:
DIS
X05:
DIS
X04:
DIS
X03:
DIS
X02:
DIS
X01:
DIS
403
reserved
X08:
DIR
X07:
DIR
X06:
DIR
X05:
DIR
X04:
DIR
X03:
DIR
X02:
DIR
X01:
DIR
404
reserved
X08:
RST
MC
OV
X07:
RST
MC
OV
X06:
RST
MC
OV
X05:
RST
MC
OV
X04:
RST
MC
OV
X03:
RST
MC
OV
X02:
RST
MC
OV
X01:
RST
MC
OV
405
reserved
X08:
RST
MC
UV
X07:
RST
MC
UV
X06:
RST
MC
UV
X05:
RST
MC
UV
X04:
RST
MC
UV
X03:
RST
MC
UV
X02:
RST
MC
UV
X01:
RST
MC
UV
406
reserved
X08:
RST
BC
OV
X07:
RST
BC
OV
X06:
RST
BC
OV
X05:
RST
BC
OV
X04:
RST
BC
OV
X03:
RST
BC
OV
X02:
RST
BC
OV
X01:
RST
BC
OV
407
reserved
X08:
RST
BC
UV
X07:
RST
BC
UV
X06:
RST
BC
UV
X05:
RST
BC
UV
X04:
RST
BC
UV
X03:
RST
BC
UV
X02:
RST
BC
UV
X01:
RST
BC
UV
408
reserved
X08:
RST
CT
X07:
RST
CT
X06:
RST
CT
X05:
RST
CT
X04:
RST
CT
X03:
RST
CT
X02:
RST
CT
X01:
RST
CT
Legend:
• DI1 INV
Pin 4: signal inversion
1 BIT
• 0x0: do not invert (default)
• 0x1: invert
• DI2 INV
Pin 2: signal inversion
1 BIT
• 0x0: do not invert (default)
• 0x1: invert
• DI1 HL
Pin 4: Signal level to be maintained
1 BIT
• 0x0: LOW
• 0x1: HIGH (default)
• DI2 HL
Pin 2: Signal level to be maintained
1 BIT
• 0x0: LOW
• 0x1: HIGH (default)
• DIS
Disable Counter: disable main c batch
counter
1 BIT
• 0x0: no action (default)
• 0x1: disable main and batch counter
• DIR
Counter Direction: Set counting direction (valid
only for counter mode CTDIR)
1 BIT
• 0x0: up (default)
• 0x1: down
• RST MC OV
Reset Main Counter Overflow: Reset counter
event overflow of the main counter
1 BIT
• 0x0: no action (default)
• 0x1: Rest overflow event
• RST MC UV
Reset Main Counter Underflow: Reset counter
event underflow of the main counter
1 BIT
• 0x0: no action (default)
• 0x1: Reset underflow event
• RST BC OV
Reset Batch Counter Overflow: Reset counter
event overflow of the batch counter
1 BIT
• 0x0: no action (default)
• 0x1: Rest overflow event
• RST BC UV
Reset Batch Counter Underflow: Reset counter
event underflow of the batch counter
1 BIT
• 0x0: no action (default)
• 0x1: Reset underflow event
• RST CT
Reset main counter and batch counter to initial
value
1 BIT
• 0x0: no action (default)
• 0x1: reset main + batch counter and
counter events to overflow/underflow