IEI Technology SPCIE-3600AM2, User Manual

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SPCIE-3600AM2 PICMG 1.3 CPU Card
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2.3.2 Processor Features
All the processors listed in the previous section support the following features:
Compatible with existing 32-bit code base
o
Including support for SSE, SSE2, SSE3*, MMX™, 3DNow!™ technology
and legacy x86 instructions
o
Runs existing operating systems and drivers
o
Local APIC on-chip
AMD64 technology
o
AMD64 technology instruction set extensions
o
64-bit integer registers, 48-bit virtual addresses, 40-bit physical
addresses
o
Eight additional 64-bit integer registers (16 total)
o
Eight additional 128-bit SSE registers (16 total)
Machine check architecture
o
Includes hardware scrubbing of major ECC protected arrays
2.3.3 L1 and L2 Cache
The L1 cache on all the processors has the following features
64 KB two-way associative ECC protected L1 data cache
o
Two 64-bit operations per cycle, 3-cycle latency
64 KB two-way associative parity-protected L1 Instruction Cache
The L2 cache sizes for the processors are listed below:
Processor L2 Cache Size
AMD Opteron™ (dual-core)
1024 KB per core
AMD Athlon™ 64 X2 (dual-core) 1024 KB or 512 KB per core
AMD Athlon™ 64 (single-core) 1024 KB, 512 KB or 256 KB
AMD Sempron™ 256 KB or 128 KB
Table 2-1: Technical Specifications