32
D800, 16k Shadow
These options enable shadowing of the contents of the ROM area
named in the option title. The settings are Enabled, Disabled, and
Cached. The ROM area not used by ISA adapter cards will be
allocated to PCI adapter cards.
DC00, 16k Shadow
These options enable shadowing of the contents of the ROM area
named in the option title. The settings are Enabled, Disabled, and
Cached. The ROM area not used by ISA adapter cards will be
allocated to PCI adapter cards.
4.6 Advanced Chipset Setup Selections
AMIBIOS SETUP – ADVANCED CHIPSET SETUP
©2001 American Megatrends Inc. All Rights Reserved
Memory Hole Disabled
SDRAM Timing by SPD Disabled
DRAM Refresh 15.6uS
DRAM Cycle time (SCLKs) 7/9
CAS# Latency (SCLKs) 3
RAS to CAS delay (SCLKs) 3
SDRAM RAS# Precharge (SCLKs) 3
Internal Graphics Mode Size 1MB
Display Cache Window Size 64MB
AGP Aperture Window 64MB
USB Function All USB Port
USB Device Legacy Support Disabled
Port 64/60 Emulation Disabled
Available Options:
> Disabled
Enabled
ESC: Exit
↑↓
: Sel
PgUp/PgDn: Modify
F1: Help
F2/F3: Color
Figure 4: Advanced Chipset Setup
Memory Hold
This field enables you to reserve an address space for ISA devices.
Configuration options: [Disabled] or [15MB-16MB].
SDRAM Timing by SPD
This sets the optimal timings for items "DRAM Refresh", "DRAM
Cycle time", "CAS# Latency", "RAS to CAS delay" and "SDRAM RAS#
Precharge", depending on the memory modules in use.
DRAM Cycle time (SCLKs)
This feature controls the number of SDRAM clocks used for SDRAM
parameters: Tras and Trc. Tras specifies the minimum clocks
required between active command and precharge command. Trc
specifies the minimum clocks required between active command and
re-active command.