IEI Technology IMBA-XQ354, User Manual

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IMBA-XQ354 Motherboard
Page 19
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Can support legacy ASF2.0.
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Integrated linear voltage regulator

TCP/UDP checksum and segmentation offload
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Receive side scaling

Wake on LAN
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Dual TX and RX queues

802.1p and 802.1q
2.6.3 Low Pin Count (LPC) Interface
The ICH9DO LPC interface complies with the LPC 1.1 specifications. The LPC bus from
the ICH9DO is connected to the following components:

iTE IT8718F super I/O chip

Fintek F81216DG serial port chip
2.6.4 PCI Interface
The PCI interface on the ICH9DO is compliant with the PCI Revision 2.3 implementation.
Some of the features of the PCI interface are listed below.

PCI Revision 2.3 compliant

33 MHz

5 V tolerant PCI signals (except PME#)

Integrated PCI arbiter supports up to four PCI bus masters
The Intel® ICH9DO is connected to three PCI expansion card slots.
2.6.5 PCIe Bus
The Intel® ICH9DO Southbridge chipset has six PCIe x1 lanes. The four PCIe lanes are
connected to the PLX PEX8518 chip, which is connected to the three PCIe x4 expansion
card slots. One PCIe x1 lane is connected to the Intel® 82573L, and another is shared
with the GLI.