IDT CPS-1848, User Manual

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CPS-1848 User Manual 197 June 2, 2014
Formal Status This document is confidential and is subject to an NDA.
Integrated Device Technology
10. Registers
This chapter discusses the CPS-1848’s configuration registers. Topics discussed include the following:
•
Overview
• Address Map
• RapidIO Capability Registers (CARs)
• RapidIO Control and Status Registers (CSRs)
• LP-Serial Extended Features Registers with Software Assisted Error Recovery
• Error Management Extensions Block Registers
• Lane Status Registers
• IDT Specific Miscellaneous Registers
• IDT Specific Event Notification Control Registers
• IDT Specific Routing Table Registers
• Trace Comparison Values and Masks Registers
• Global Device Configuration Registers
• Implementation Specific Multicast Mask Registers
• Port Function Registers
• Implementation Specific Error Logging Registers
• Special Error Registers
• PLL Registers
• Lane Control Registers
• Error Management Broadcast Registers
10.1 Overview
The CPS-1848 register file is addressable through I
2
C, JTAG, and any RapidIO port, and is built with 22-bit addresses and
32-bit words, as specified by the RapidIO Specification (Rev. 2.1). All unused address space should be considered
RESERVED.
10.1.1 RapidIO Compliance
The CPS-1848 is compliant to the RapidIO Specification (Rev. 2.1) . The device supports the “Generic: All devices”
requirements in the RapidIO Specification (Rev. 2.1), Part 7: System and Device Interoperability Specification. This
requirement suggests support for a number of RapidIO-specific registers. The CPS-1848 supports each of these registers
except for the “Destination Operations CAR”. The RapidIO Specification (Rev. 2.1), Part 1: Input/Output Logical Specification
defines this register as being applicable to switches only.