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©2017 Integrated Device Technology, Inc.
October 20, 2017
9FGV1006 Register Descriptions and Programming Guide
Fractional Feedback Divider and Spread Spectrum
Spread spectrum capability is contained within the Fractional-N feedback divider associated with the PLL. When applied, triangle wave
modulation of any spread spectrum amount, SS%AMT up to ±2.5% center spread and -5% down spread between 30 and 63kHz may be
generated, independent of the output clock frequency. Five variables define spread spectrum in the FFD (see
).
Equations
:
To calculate the spread spectrum registers, first determine the value in decimal of the FFD output divider P. The value of P will be the top
of the triangle modulation wave. In case of Down Spread, this is perfect so we can use P as is. In case of Center Spread, we need to
offset P.
Down spread:
— FFD value P = INT(P) + FRAC(P) = FVCO / (2 × FPFD) (4)
— See equations 2 and 3 in section
Fractional Output Divider Configuration
for address 0x12, 0x13 and 0x14 settings.
Center spread
:
— FFD value P = INT(P) + FRAC(P) = (1 - SS% / 200) × (FVCO / (2 × FPFD)) (5)
— Note that the SS% value is the peak-to-peak value. so with ±1.0% center spread, the SS% value is 2.0%
Consider one cycle of down spread triangular modulation; the FFD value is ramped down linearly from the P value followed by a linear
ramp back up to the value of P. The modulated value of the FFD is always smaller than or equal to the value of P.
Table 4. Spread Spectrum Variables in the FFD
Name
Function
RAM Register
Note
SS Enable
Spread spectrum control enable
0x10 [7].
When SS Enable = 0, contents of Period and
Step registers are Don't Care.
When SS Enable = 1, enables the spread
spectrum modulation.
FOD Integer
Integer portion of the FOD value P
0x12 [7..0].
See equations 4 and 5 below.
FOD Fraction Fractional portion of the FOD value P
0x13 [7..0] = Fraction [15..8].
0x14 [7..0] = Fraction [7..0].
See equations 4 and 5 below.
SS Period
Spread spectrum modulation period
0x10 [3..0] = Period [11..8].
0x11 [7..0] = Period [7..0].
Total 12-bits for the period.
Defined as half the reciprocal of the modulation
frequency and measured in cycles of the FFD
output frequency. See equation 6
below.
SS Step
Modulation step size
0x15 [7..0] = Step [15..8].
0x16 [7..0] = Step [7..0].
Sets the time rate of change or time slope of the
output clock frequency. See equation. 8 below.