IDT 9FGV1006, Register Descriptions And Programming Manual, Page: 6 / 12

6 ©2017 Integrated Device Technology, Inc. October 20, 2017
9FGV1006 Register Descriptions and Programming Guide
14 0x0E
7 1 Crystal oscillator LDO: 0 = disabled, 1 = enabled.
6 0 Reserved.
[5..0] 000101
Crystal oscillator X1 pin capacitance: Cap (pF) = 10 + 0.44 × Bits[4..0] + 7.04
× Bit[5].
See section
Crystal Load Capacitance Registers for crystal oscillator load
capacitance configuration.
15 0x0F
7 1 Crystal oscillator circuit: 0 = Disabled, 1 = Enabled.
6 0 Reserved.
[5..0] 000101
Crystal oscillator X2 pin capacitance: Cap (pF) = 7.98 + 0.442 × Bits[4..0] +
7.072 × Bit[5].
16 0x10
7 0
Fractional feedback divider (FFD) spread spectrum: 0 = disabled, 1 =
enabled.
[6..4] 000 Reserved.
[3..0] 0000
FFD spread spectrum period, bits[11..8]. See section Fractional Feedback
Divider and Spread Spectrum for spread spectrum configuration.
17 0x11 [7..0] 00-hex FFD spread spectrum period, bits[7..0].
18 0x12 [7..0] 0C-hex
FFD integer value. See section Fractional Output Divider Configuration for
fractional feedback divider configuration.
19 0x13 [7..0] 80-hex FFD fractional value, bits[15..8].
20 0x14 [7..0] 00-hex FFD fractional value, bits[7..0].
21 0x15 [7..0] 00-hex FFD spread spectrum step, bits[15..8].
22 0x16 [7..0] 00-hex FFD spread spectrum step, bits[7..0].
23 0x17 [7..0] 00-hex Reserved.
24 0x18
7 1
FFD reset-B: 0 = hold FFD in reset mode, 1 = release FFD.
Toggle to 0 and back to 1 to apply a reset or restart of the FFD.
[6..2] 00000 Reserved.
1 0
FFD integer mode: 0 = use fractional settings for a fractional feedback divider
value.
1 = run feedback divider in integer mode in case the value is an integer (for
best performance).
0 1 Enable FFD: 0 = FFD is disabled, 1 = FFD is enabled.
25 0x19 [7..0] 00-hex Reserved.
Table 3. RAM Register Map (Cont.)
Register Address
Register Bit Default Function Description
Decimal Hex