IDT 89HPES24N3A, User Manual

Page: 68 / 168

IDT SMBus Interfaces
PES24N3A User Manual 6 - 2 April 10, 2008
Notes
In the split configuration, the master and slave SMBuses operate as two independent buses. Thus,
multi-master arbitration is not required.
Master SMBus Interface
The master SMBus interface is used during a fundamental reset to load configuration values from an
optional serial EEPROM. It is also used to support optional I/O expanders used for hot-plug and other
status signals.
Initialization
Master SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page
2-4). During a fundamental reset initialization sequence, the state of the Master SMBus Slow Mode
(MSMBSMODE) signal is examined. If this signal is asserted, then the Master SMBus Clock Prescalar
(MSMBCP) field in the SMBus Control (SMBUSCTL) register is initialized to support 100 KHz SMBus oper-
ation. If the signal is negated, then the MSMBCP field is initialized for 400 KHz SMBus operation.
Serial EEPROM
During a fundamental or hot reset, an optional serial EEPROM may be used to initialize any software
visible register in the device. Serial EEPROM loading occurs if the Switch Mode (SWMODE[3:0]) field
selects an operating mode that performs serial EEPROM initialization. The address used by the SMBus
interface to access the serial EEPROM is specified by the MSMBADDR[4:1] signals as shown in Table 6.1.
Device Initialization from a Serial EEPROM
During initialization from the optional serial EEPROM, the master SMBus interface reads configuration
blocks from the serial EEPROM and updates corresponding registers in the PES24N3A. Any PES24N3A
software visible register in any port may be initialized with values stored in the serial EEPROM.
Each software visible register in the PES24N3A has a CSR system address which is formed by adding
the PCI configuration space offset value of the register to the base address of the configuration space in
which the register is located. Configuration blocks stored in the serial EEPROM use this CSR system
address shifted right two bits (i.e., configuration blocks in the serial EEPROM use doubleword CSR system
addresses and not byte CSR system addresses).
Base addresses for the PCI configuration spaces in the PES24N3A are listed in Table 9.1 of Chapter 9.
Since configuration blocks are used to store only the value of those registers that are initialized, a serial
EEPROM much smaller than the total size of all of the configuration spaces may be used to initialize the
device.
Any serial EEPROM compatible with those listed in Table 6.2 may be used to store the PES24N3A
initialization values. Some of these devices are larger than the total size of all of the PCI configuration
spaces in the PES24N3A that may be initialized and thus may not be fully utilized.
Address Bit Address Bit Value
1 MSMBADDR[1]
2 MSMBADDR[2]
3 MSMBADDR[3]
4 MSMBADDR[4]
5 1
6 0
7 1
Table 6.1 Serial EEPROM SMBus Address