IDT 89HPES24N3A, User Manual

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Notes
PES24N3A User Manual 9 - 1 April 10, 2008
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Chapter 9
Configuration Registers
Introduction
Each software-visible register in the PES24N3A is contained in the PCI configuration space of one of the
ports. Thus, there are no registers in the PES24N3A that cannot be accessed by the root. Each software-
visible register in the PES24N3A has a system address. The system address is formed by adding the PCI
configuration space offset value of the register to the base address of the port in which it is located. The
system address is used for serial EEPROM register initialization and slave SMBus register accesses.
The base address for each PES24N3A port is listed in Table 9.1. The PCI configuration space offset
addresses for registers in the upstream port are listed in Table 9.2 while the PCI configuration space offset
addresses for registers in downstream ports are listed Table 9.3.
As shown in Figure 9.1, upstream and downstream ports share a similar PCI configuration space
register layout. The upstream port contains global switch control and status registers as well as test mode
registers which are not present in the configuration space of downstream ports. Due to the ability to
generate MSIs as a result of hot-plug events, the downstream ports contain an MSI capability structure
which is not present in the upstream port.
PCIe configuration reads to an upstream port offset not defined in Table 9.2 or a downstream port offset
not defined in Table 9.3 return a value of zero. Slave SMBus reads to these offsets return an undefined data
value. PCIe configuration writes or Slave SMBus writes to an offset not defined in Table 9.2 or Table 9.3
complete successfully but modify no data and have no other effect.
Base
Address
PCI Configuration Space
0x0000 Port 0 configuration space (upstream port)
0x2000 Port 2 configuration space (downstream port)
0x4000 Port 4 configuration space (downstream port)
Table 9.1 Base Addresses for Port Configuration Space Registers