IDT 89HPES16NT2, User Manual

Page: 93 / 292

IDT Transparent Mode Operation
PES16NT2 User Manual 9 - 7 April 15, 2008
Notes
Upstream Port A Configuration Space Registers
All configuration space locations not listed in Table 9.5 return a value of zero when read. Writes to these
locations are ignored and have no side-effects. Port A configuration space registers may be read and
written via the slave SMBus interface and initialized from the serial EEPROM using the CSR system
address formed by adding the base address 0x0000 to the PCI configuration space offset address.
Note: In pdf format, clicking on a register name in the Register Definition column creates a jump
to the appropriate register. To return to the starting place in this table, click on the same register
name (in blue) in the register section.
Cfg.
Offset
Size
Register
Mnemonic
Register Definition
0x000 Word PA_VID PA_VID - Vendor Identification (0x000) on page 9-9
0x002 Word PA_DID PA_DID - Device Identification (0x002) on page 9-9
0x004 Word PA_PCICMD PA_PCICMD - PCI Command (0x004) on page 9-9
0x006 Word PA_PCISTS PA_PCISTS - PCI Status (0x006) on page 9-10
0x008 Byte PA_RID PA_RID - Revision Identification (0x008) on page 9-11
0x009 3 Bytes PA_CCODE PA_CCODE - Class Code (0x009) on page 9-12
0x00C Byte PA_CLS PA_CLS - Cache Line Size (0x00C) on page 9-12
0x00D Byte PA_PLTIMER PA_PLTIMER - Primary Latency Timer (0x00D) on page 9-12
0x00E Byte PA_HDR PA_HDR - Header Type (0x00E) on page 9-12
0x00F Byte PA_BIST PA_BIST - Built-in Self Test (0x00F) on page 9-12
0x010 DWord PA_BAR0 PA_BAR0 - Base Address Register 0 (0x010) on page 9-13
0x014 DWord PA_BAR1 PA_BAR1 - Base Address Register 1 (0x014) on page 9-13
0x018 Byte PA_PBUSN PA_PBUSN - Primary Bus Number (0x018) on page 9-13
0x019 Byte PA_SBUSN PA_SBUSN - Secondary Bus Number (0x019) on page 9-13
0x01A Byte PA_SUBUSN PA_SUBUSN - Subordinate Bus Number (0x01A) on page 9-13
0x01B Byte PA_SLTIMER PA_SLTIMER - Secondary Latency Timer (0x01B) on page 9-13
0x01C Byte PA_IOBASE PA_IOBASE - I/O Base (0x01C) on page 9-14
0x01D Byte PA_IOLIMIT PA_IOLIMIT - I/O Limit (0x01D) on page 9-14
0x01E Word PA_SECSTS PA_SECSTS - Secondary Status (0x01E) on page 9-14
0x020 Word PA_MBASE PA_MBASE - Memory Base (0x020) on page 9-15
0x022 Word PA_MLIMIT PA_MLIMIT - Memory Limit (0x022) on page 9-15
0x024 Word PA_PMBASE PA_PMBASE - Prefetchable Memory Base (0x024) on page 9-
15
0x026 Word PA_PMLIMIT PA_PMLIMIT - Prefetchable Memory Limit (0x026) on page 9-
16
0x028 DWord PA_PMBASEU PA_PMBASEU - Prefetchable Memory Base Upper (0x028) on
page 9-16
0x02C DWord PA_PMLIMITU PA_PMLIMITU - Prefetchable Memory Limit Upper (0x02C) on
page 9-16
0x030 Word PA_IOBASEU PA_IOBASEU - I/O Base Upper (0x030) on page 9-17
Table 9.5 Upstream Port A Configuration Space Registers (Part 1 of 3)