IDT 89HPES16NT2, User Manual

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IDT Transparent Mode Operation
PES16NT2 User Manual 9 - 10 April 15, 2008
Notes
PA_PCISTS - PCI Status (0x006)
2 BME RW 0x0 Bus Master Enable. When this bit is cleared, the bridge
does not issue requests (e.g., memory, I/O and MSIs since
they are in-band writes) on behalf of subordinate devices
and responds to non-posted transactions with a Unsup-
ported Request (UR) completion. This bit does not affect
completions in either direction or the forwarding of non
memory or I/O requests.
0x0 - (disable) Disable request forwarding.
0x1 - (enable) Enable request forwarding.
3 SSE RO 0x0 Special Cycle Enable. Not applicable.
4 MWI RO 0x0 Memory Write Invalidate. Not applicable.
5 VGAS RO 0x0 VGA Palette Snoop . Not applicable.
6 PERRE RW 0x0 Parity Error Enable. The Master Data Parity Error bit is
set in the PCI Status register (PCISTS) if this bit is set and
the bridge receives a poisoned completion or a poisoned
write. If this bit is cleared, then the Master Data Parity Error
bit in the PCI Status register is never set.
0x0 - (disable) Disable Master Parity Error bit reporting.
0x1 - (enable) Enable Master Parity Error bit reporting.
7 ADSTEP RO 0x0 Address Data Stepping. Not applicable.
8 SERRE RW 0x0 SERR Enable. Non-fatal and fatal errors detected by the
bridge are reported to the Root Complex when this bit is set
or the bits in the PCI Express Device Control register are
set (see PA_PCIEDCTL - PCI Express Device Control
(0x048)).
0x0 - (disable) Disable non-fatal and fatal error reporting if
also disabled in Device Control register.
0x1 - (enable) Enable non-fatal and fatal error reporting.
9 FB2B RO 0x0 Fast Back-to-Back Enable. Not applicable.
10 INTXD RW 0x0 INTx Disable. Controls the ability of the PCI-PCI bridge to
generate an INTx interrupt message.
15:11 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
2:0 Reserved RO 0x0 Reserved field.
3 INTS RO 0x0 INTx Status. This bit is set when an INTx interrupt is pend-
ing from the device.
INTx emulation interrupts forwarded by switch ports from
devices downstream of the bridge are not reflected in this
bit.
For all ports, this field is always zero.
Bit
Field
Field
Name
Type
Default
Value
Description