IDT 89HPES16NT2, User Manual

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IDT Transparent Mode Operation
PES16NT2 User Manual 9 - 20 April 15, 2008
Notes
PA_PCIEDCTL - PCI Express Device Control (0x048)
13 AIP RWL 0x0 Attention Indicator Present. When set, this bit indicates
that an Attention Indicator is implemented on the card/mod-
ule. This bit should not be set on downstream ports.
14 PIP RWL 0x0 Power Indicator Present. When set, this bit indicates that
a Power Indicator is implemented on the card/module. This
bit should not be set on downstream ports.
25:18 CSPLV RO 0x0 Captured Slot Power Limit Value. (Upstream Port A only,
hardwired to zero in downstream ports) Captured Slot
Power Limit Value (upstream Ports only, hardwired to zero
in downstream ports) – In combination with the Slot Power
Limit Scale value, specifies the upper limit on power sup-
plied by slot.Power limit (in Watts) calculated by multiplying
the value in this field by the value in the Slot Power Limit
Scale field.
This value is set by the Set_Slot_Power_Limit Message.
27:26 CSPLS RO 0x0 Captured Slot Power Limit Scale. (Upstream Port A only,
hardwired to zero in downstream ports) This field specifies
the scale used for the Slot Power Limit Value and is set via
a Set_Slot_Power_Limit message.
0 - (v1) 1.0x
1 - (v1p1) 0.1x
2 - (v0p01) 0.01x
3 - (v0p001x) 0.001x
31:28 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
0 CEREN RW 0x0 Correctable Error Reporting Enable . This bit controls
reporting of correctable errors.
1 NFEREN RW 0x0 Non-Fatal Error Reporting Enable . This bit controls
reporting of non-fatal errors.
2 FEREN RW 0x0 Fatal Error Reporting Enable . This bit controls reporting
of fatal errors.
3 URREN RW 0x0 Unsupported Request Reporting Enable . This bit con-
trols reporting of unsupported requests.
4 ERO RO 0x0 Enable Relaxed Ordering . When set, this bit enables
relaxed ordering. The switch never sets the relaxed order-
ing bit in transactions it initiates as a requester.
Bit
Field
Field
Name
Type
Default
Value
Description