IDT 89HPES16NT2, User Manual

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Notes
PES16NT2 User Manual 4 - 1 April 15, 2008
®
Chapter 4
Switch Operation
Introduction
The PES16NT2 utilizes an input buffered cut-through switch to forward PCIe® TLPs between switch
ports. At a high level the switch may be viewed as consisting of three PCIe stacks and a switch core. The
PCIe stacks are each responsible for performing the per port Phy, data link and transaction layer functions
defined in the PCIe specification. The switch core is responsible for maintaining routing information in route
map tables, maintaining per port ingress and egress flow control information, buffering TLPs, and
forwarding TLPs between stacks.
The buffering and data flow of the switch is graphically depicted in Figure 4.1 below. Note that an ingress
stack can transfer a TLP to its own egress stack through the switch core. This path is necessary since all
transactions in the PES16NT2 are routed through the switch core, even those that could be satisfied locally,
due to the fact that the switch core is responsible for maintaining flow control information.
Figure 4.1 PES16NT2 Switch Data Flow and Buffering
TLPs are received by a port stack and passed to the switch core. Associated with each port in the switch
core are three input buffers: One for posted transactions, one for non-posted transactions and one for
completions. The size of each of these buffers is shown in Table 4.1. Associated with each TLP in a buffer is
a descriptor. Thus, a buffer has a limitation on the total number of TLPs that can be stored as well as on the
number of bytes.
Buffer Size and Limitations
Posted FIFO 4 KB and up to 32 TLPs
Non-posted FIFO 1 KB and up to 32 TLPs
Completions FIFO 4 KB and up to 32 TLPs
Egress Stack Replay Buffer
1
1.
Stored with each TLP is a 32-bit LCRC as well as other information.
5120 bytes and up to 15 TLPs
Table 4.1 PES16NT2 Buffer Sizes
Posted FIFO
Replay Buffer
Port A Stack
Egress Functions
Port A Stack
Ingress Functions
Non-Posted FIFO
Completion FIFO
Port A
Link
Input
Port A
Link
Output
Posted FIFO
Replay Buffer
Port C Stack
Egress Functions
Port C Stack
Ingress Functions
Non-Posted FIFO
Completion FIFO
Port C
Link
Input
Port C
Link
Output