IDT Installation of the EB12N3 Eval Board
Boot Configuration Vector
EB12N3 Eval Board Manual (18-597-001)
2 - 7
November 2, 2006
Notes
Boot Configuration Vector
A Boot Configuration Vector consisting of the signals listed in Table 2.10 is sampled by the PES12N3
during a fundamental reset (while PERSTN is active). The Boot Configuration Vector defines the essential
parameters for switch operation and is set using DIP Switches J1 and J2 as defined in Table 2.11
Port#
Header
Selection
B
J11
[1-2] PGOOD_B_N controlled reset (used when hot-plugging is enabled)
[3-4] Software controlled reset through GPIO0
[5-6] Fundamental reset PERST# (default)
C
J12
[1-2] PGOOD_C_N controlled reset (used when hot-plugging is enabled)
[3-4] Software controlled reset through GPIO1
[5-6] Fundamental reset PERST# (default)
Table 2.9 Downstream Reset Selection
Boot Configuration Vector Signals
Signal
Description
CCLKDS
Common Clock Downstream.
The assertion of this pin indicates that all downstream
ports are using the same clock source as that provided to downstream devices. This
pin is used as the initial value of the Slot Clock Configuration bit in all of the Link Status
Registers for downstream ports. The value may be overridden by modifying the SCLK
bit in the PB_PCIELSTS or PC_PCIELSTS register.
Default: 0x1
CCLKUS
Common Clock Upstream.
The assertion of this pin indicates that the upstream port
is using the same clock source as the upstream device. This pin is used as the initial
value of the Slot Clock Configuration bit in the Link Status Register for the upstream
port. The value may be overridden by modifying the SCLK bit in the PA_PCIELSTS
register.
Default: 0x1
MSMBSMODE
Master SMBus Slow Mode.
The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 kHz.
Default: 0x0
PEALREV
PCI Express Port A Lane Reverse.
When this pin is asserted, the lanes of PCI
Express Port A are reversed. This value may be overridden by modifying the value of
the PALREV bit in the PA_SWCTL register.
Default: 0x0
PEBLREV
PCI Express Port B Lane Reverse.
When this pin is asserted, the lanes of PCI
Express Port B are reversed. This value may be overridden by modifying the value of
the PBLREV bit in the PA_SWCTL register.
Default: 0x0
PECLREV
PCI Express Port C Lane Reverse.
When this pin is asserted, the lanes of PCI
Express Port C are reversed. This value may be overridden by modifying the value of
the PCLREV bit in the PA_SWCTL register.
Default: 0x0
REFCLKM
PCI Express Reference Clock Mode Select.
These signals select the frequency of
the reference clock input.
Default: 0x0
0x0 - 100 MHz
0x1 - 125 MHz
Table 2.10 Boot Configuration Vector Signals (Part 1 of 2)
Summary of Contents for 89EBPES12N3
Page 4: ...IDT Table of Contents EB12N3 Eval Board Manual 18 597 001 ii November 2 2006 Notes...
Page 6: ...IDT List of Tables EB12N3 Eval Board Manual 18 597 001 iv November 2 2006 Notes...
Page 8: ...IDT List of Figures EB12N3 Eval Board Manual 18 597 001 iv November 2 2006 Notes...
Page 31: ...Notes EB12N3 Eval Board Manual 18 597 001 4 1 November 2 2006 Chapter 4 Schematics Schematics...
