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iO1000 Detailed Service Manual - THEORY OF OPERATION
DSP Phase Locked Loop (PLL)
The DSP phase locked loop (PLL) is programmable and is used to generate a DSP
internal clock that is synchronized to the 16.8 MHz reference frequency. In low
power mode, the DSP PLL is disabled and the DSP operates directly from the
16.8 MHz clock. During initial power up of the radio, the DSP initially operates
directly from the 32.768 kHz clock until the LV Frac-N is programmed for 16.8
MHz and the DSP PLL is programmed to generate a higher operating frequency.
The DSP PLL runs at 58.8 MHz.
Host System Clock Synthesizer
During initial power up, the host system clock (RCE) is synthesized from the
32.768 kHz crystal via the GCAP II using the built-in GCAP PLL. The host
microprocessor’s system clock is then referenced from the LV Frac-N 16.8 MHz
reference. The RCE programmable interrupt timer (PIT) is run by the 32.768 kHz
oscillator.
Connectors
The modem includes three connectors:
¥
J2, a surface-mount RF connector locatred on the RF board .
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J4, a 30-pin host interface connector (described below).
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J1/P1, the 60-pin RF-to logic board connector (described below).
