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5-2 PCI-AOB2/4/6 Series User’s Guide
Restrict-Output-Voltage
Limits the output of all DAC channels and is active at power-up. This is done by reading
Base E. The previous outputs will be restored when a "Clear
Restrict-Output-Voltage" command is issued by a read of Base F.
External Trigger Update Mode
Allows a negative level at pin 25 of the I/O connector to cause the DACs to be updated. A
read of Base 5 will enable this mode, a read of Base 6 will disable it.
Note that this pin is shared with the External Interrupt signal.
External Interrupt
A negative edge at pin 25 and is latched until cleared by a read of Base 4. The
interrupt is enabled by a read of Base 3 and powers up disabled. After being
cleared the interrupt must be re-enabled.
Table 5-1. PCI-AOB2/4/6 Series Register Map
Address
Write *
Read
Base + 0
DAC 0 Low Byte
Place card in Simultaneous Mode without
updating outputs.
Base + 1
DAC 0 High Byte
not used
Base + 2
DAC 1 Low Byte
Release card from Simultaneous Mode
without updating outputs.
Base + 3
DAC 1 High Byte
Enable External Interrupts
Base + 4
DAC 2 Low Byte
Disable External Interrupts
Base + 5
DAC 2 High Byte
Enable External DAC Update
Base + 6
DAC 3 Low Byte
Disable External DAC Update
Base + 7
DAC 3 High Byte
not used
Base + 8
DAC 4 Low Byte
Update all outputs and place card in
Simultaneous Mode.
Base + 9
DAC 4 High Byte
not used
Base + A
DAC 5 Low Byte
Update all outputs and release card from
Simultaneous Mode.
Base + B
DAC 5 High Byte
not used
Base + C
not used
not used
Base + D
not used
not used
Summary of Contents for PCI-AOB2 Series
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