ICS Advent WDT1000-P, Product Manual

Page: 23 / 34

Chapter 5: Programming
Manual Number: 00650-009-28 Page 5-3
Mode 1: Retriggerable One-Shot
The output goes low on the clock pulse following a trigger to begin theone-shot pulse and goes high
when the counter reaches zero. Additional triggers result in reloading the count and starting the
cycle over. If a trigger occurs before the counter decrements to zero, a new count is loaded. Thus,
this forms a re-triggerable one-shot. In mode 1, a low output pulse is provided with a period equal
to the counter count-down time.
Mode 2: Rate Generator
This mode provides a divide-by-N capability where N is the count loaded into the counter. When
triggered, the counter output goes low for one clock period after N counts, reloads the initial count,
and the cycle starts over. This mode is periodic, the same sequence is repeated indefinitely until the
gate input is brought low.
Mode 3: Square Wave Generator
This mode operates periodically like mode 2. The output is high for half of the count and low for the
other half. If the count is even, then the output is a symmetrical square wave. If the count is odd,
then the output is high for (N+1)/2 counts and low for (N-1)/2 counts. Periodic triggering or fre-
quency synthesis are two possible applications for this mode.
Mode 4: Software Triggered Strobe
This mode sets the output high and, when the count is loaded, the counter begins to count down.
When the counter reaches zero, the output will go low for one input period. The counter must be
reloaded to repeat the cycle. A low gate input will inhibit the counter.
Mode 5: Hardware Triggered Strobe
In this mode, the counter will start counting after the rising edge of the trigger input and will go low
for one clock period when the terminal count is reached. The counter is re-triggerable. The output
will not go low until the full count after the rising edge of the trigger.
In order to program the Watchdog circuit, consider the following code:
WDBASE% = &H300 'Set watchdog base address to 'hex300.
OUT WDBASE% + 3, &H90 'Set counter 2 to mode 0,
'Read/Load Least Sig. Byte,
'Mode 0, binary.
OUT 2, 100 'Load Counter 2 Low Byte
'100*4.44mSec.
COMBASE% = &H3F8 'Set serial commun’n base 'address as com1 (3F8).
MCR% = INP(C4) 'Read modem control register at 'C 4.
OUT C4,MCR% OR 4 'Enable watchdog controlled by 'bit 2 of modem
control 'register without changing the 'remaining bits.