PEX/PIO/PISO-DA Series Card
Analog Output Boards
User Manual/ Ver. 3.1/ Oct. 2013/ PMH-0010-31/ Page: 23
2.4.2
D/O Port Architecture (CON1)
When the PC is powered up, the states of all DO channels are cleared low. The RESET\ signal
is used to clear the DO states. Refer to
Sec. 6.3.1
for more information about the RESET\
signal.
The RESET\ signal is in the Low-state
all DO channels are cleared to the low state
The block diagram of DO is as follows:
D/O buffer CKT
Clock input
input
Latch
Data
RESET\
CON1
clear
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