ICP DAS USA ECAT-2092T, User Manual

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The slave operates autonomously based on its own cycle and is not synchronized with
the EtherCAT cycle.
The master cycle time and the slave cycle time are fully independent which
means each slave device reads/writes its own process data according to its local time,
independent of the master’s cycle time.
Figure 13: Master-slave cycle in Free Run mode
The following diagram shows the process timing of the slave in Free Run mode in detail:
Figure 14: Slave processing sequence in Free-run mode
The slave firmware checks in each cycle time the memory of the EtherCAT slave chip
(ESC) whether new output data has been received from the master. Newly received data
will be processed. In the next step the encoder input status are being read from the
FPGA chip. In the final step the read status are being written to the DPRAM, so that the
master can retrieve the data ESC DPRAM in the next cycle time.
ICP DAS Page ECAT-2092T User Manual
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