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3 - 6
3-3 PLL CIRCUIT
3-3-1 GENERAL
The PLL unit generates a 1st LO frequency (69.5115-
99.0114 MHz), 2nd LO frequency (60 MHz) and a BFO fre-
quency (9.0106–9.013 MHz) for the MAIN unit. The 1st LO
PLL adopts a mixerless dual loop PLL system. The BFO
uses a DDS and a 2nd LO as a fixed frequency double that
the crystal oscillator.
3-3-2 1ST LO PLL (PLL UNIT)
The 1st LO PLL contains a main loop and reference loop as
a dual loop system. The reference loop generates a 10.65 to
10.75 MHz frequency using a DDS circuit, and the main loop
generates a 69.5115 to 99.0114 MHz frequency using the
reference loop frequency.
(1) REFERENCE LOOP PLL
The oscillated signal at the reference VCO (Q5, D3) is
amplified at the buffer amplifiers (Q6, Q11) and is then
applied to the DDS IC (IC1, pin 46). The signal is then divid-
ed and detected on phase with the DDS generated frequen-
cy.
The detected signal output from IC1 (pin 56) is converted
into a DC voltage (lock voltage) at the loop filter (R18, R19,
C 44) and then fed back to the varactor diode (D3) in the
VCO circuit.
(2) MAIN LOOP PLL
The oscillated signal at the main loop VCO (Q3, D4) is
amplified at the buffer amplifiers (Q4, Q8) and is then
applied to the PLL IC (IC5, pin 14). The signal is then divid-
ed and detected on phase with the reference loop output fre-
quency.
The detected signal output from IC5 (pins 9, 10) is convert-
ed into a DC voltage (lock voltage) at the loop filter and then
fed back to the varactor diode (D4) in the VCO circuit.
The oscillated signal is amplified at the buffer amplifiers (Q4,
Q21, Q24) and then applied to the MAIN unit as a 1st LO
signal.
3-3-3 2ND LO AND REFERENCE OSCILLATOR
CIRCUITS
The reference oscillator (X1) generates 30.0 MHz frequency
used for the both DDS ICs as a system clock and for the LO
output. The oscillated signal is doubled at the driver (Q2)
and picked up the 60 MHz frequency at the resonator circuit
(L4, L5). The 60 MHz signal is applied to the MAIN unit as a
2nd LO signal.
3-3-4 BFO CIRCUIT
The DDS IC (IC2) generates a 10-bit digital signal using the
30 MHz system clock. The digital signal is converted to an
analog wave signal at the D/A converter (R120–R139). The
analog wave is passed through the low-pass filter (L37, L38,
C154–C158) and is then applied to the MAIN unit as the
BFO signal.
1
10
11
16
17
21
22
23
24
25
26
27
28
30
31
33
34
36
37
39
41
42
48
Input port for the CPU reset signal.
When receiving a “LOW” pulse, the
CPU is reset.
Data input port from the sub CPU in
the controller.
Data output port to the sub CPU in the
controller.
Outputs low power control signal for
60 W power.
Outputs low power control signal for
20 W power.
Outputs a “SEND” control signal for
the ACC socket.
Outputs a “SEND” control signal for T8
and R8 voltage line control.
Low : for transmit.
Outputs an alarm control signal to acti-
vate the 2-tone emergency alarm
encoder.
High : alarm on
Outputs a tone switching signal for the
2-tone emergency alarm encoder.
High : high tone
Outputs a clock signal for the EEP-
ROM (IC46).
IInput port for serial signal from the
EEPROM (IC46).
Outputs serial signal for the EEPROM
(IC46).
Outputs select signal for the EEPROM
(IC46).
Input port for the S-meter indication.
Input port for the RF-meter indication.
Input port for the squelch detected sig-
nal.
High : when squelch is open.
Input port for the transmit/receive
switching signal.
Outputs RF gain control signal to the
AGC circuit.
CW keying input.
High : when key is closed.
Outputs AF gain control signal to the
controller.
Outputs a strobe signal to the main
loop PLL IC (IC5).
Outputs a strobe signal to the refer-
ence loop DDS IC (IC1).
Outputs a strobe signal to the BFO
PLL IC (IC2).
3-4 PORT ALLOCATIONS
3-4-1 CPU (MAIN unit; IC44)
RES
RXDO
TXDO
POC2
POC1
ASEN
CSEN
ALMS
ALMC
SCK
SI
SO
CS
RSM
MFOR
SQLS
TRC
RFG
CWIN
AFG
STB1
STB2
STB3
Pin
Port
Description
number
name