4 - 3
4-2-3 DRIVE AMPLIFIER CIRCUIT (MAIN unit)
The drive amplifier circuit amplifies the VCO oscillating sig-
nal to the level needed at the power amplifier.
The RF signal from the buffer amplifier (Q30) passes
through the T/R switch (D18) and is amplified at the buffer
(Q21, Q20) and drive (Q19) amplifiers. The amplified signal
is applied to the power amplifier circuit.
4-2-4 POWER AMPLIFIER CIRCUIT (MAIN unit)
The power amplifier circuit amplifies the driver signal to an
output power level.
The RF signal from the drive amplifier (Q19) is applied to the
power module (IC5) to obtain 35 W (for IC-F420/F420S; 25
W for IC-F410/F410S) of RF power.
The amplified signal is passed through the antenna switch-
ing circuit (D3), low-pass filter and APC detector, and is then
applied to the antenna connector.
Collector voltages for the driver (Q19) and control voltage
for the power amplifier (IC5, pin 2) come from the APC con-
troller (Q17, Q18) to stabilize the output power. The transmit
mute switch (Q16) controls the APC controller when transmit
mute is necessary.
4-2-5 APC CIRCUIT (MAIN unit)
The APC circuit protects the power amplifier from a mis-
matched output load and stabilizes the output power.
The APC detector circuit (D1) detects forward signals and
reflection signals. The combined voltage is at minimum level
when the antenna impedance is matched at 50
Ω
and is
increased when it is mismatched.
The detected voltage is applied to the inverse amplifier
(IC4b, pin 6), and the power setting voltage (T4) is applied
to the other input (pin 5) for the reference. When antenna
impedance is mismatched, the detected voltage exceeds
the power setting voltage. The output voltage of the inverse
amplifier (IC4b, pin 7) controls the input current of the power
module (IC5) and drive amplifier (Q19) to reduce the output
power via the APC controller (Q17, Q18).
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL circuit con-
sists of the PLL IC (IC2), loop filter and reference oscillator
circuit and employs a pulse swallow counter.
An oscillated signal from the VCO (Q23, Q25) passes
through the buffer amplifiers (Q28, Q29), is applied to the
PLL IC (IC10, pin 2) and is prescaled in the PLL IC based on
the divided ratio (N-data). The reference signal is generated
at the reference oscillator (X2) and is also applied to the PLL
IC. The PLL IC detects the out-of-step phase using the ref-
erence frequency and outputs it from pin 8. The output sig-
nal is passed thorough the loop filter (Q34, R180, R181,
C203, C231) and is then applied to the VCO circuit as the
lock voltage.
4-3-2 VCO CIRCUIT (MAIN unit)
The VCO circuit contains a separate RX VCO (Q23, D20,
D34) and TX VCO (Q25, D22, D33). The oscillated signal is
amplified at the buffer amplifiers (Q28, Q29) and is then
applied to the T/R switching circuit (D18, D19). The Rx sig-
nal is applied to the 1st mixer circuit (Q3) and the Tx signal
to the driver (Q19) via the buffer amplifers (Q21, Q20).
A portion of the signal from Q28 is amplified at the buffer
amplifier (Q29) and is then fed back to the PLL IC (IC10,
pin 2).
• PLL circuit
Shift register
×
3
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
X1
15.3 MHz
45.9 MHz signal
to the FM IF IC
15
Q23, D20, D34
RX VCO
TX VCO
Buffer
Buffer
Buffer
Q30
Q29
Q28
3
4
5
PLST
IC10 (PLL IC)
SCK
SO
to transmitter circuit
to 1st mixer circuit
D19
D18
17
8
2
Q25, D22, D33
