iC-Haus iC-TW29 Manual Download Page 7 | Manualshive

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iC-TW29

26-BIT ENCODER PROCESSOR

WITH INTERPOLATION AND BiSS INTERFACE

Rev C1, Page 7/28

PIN FUNCTIONS

No. Name

I/O

Function

Description

29 SI

Digital in

SPI Slave Input

Connect to SPI master MO pin.

30 SCLK

Digital in

SPI Slave Clock Input

Connect to SPI master clock output pin.

31 xSS

Digital in

SPI Slave Select Input

Connects to SPI master slave select output pin.

32 BISSEN

Digital in

BiSS Interface Enable

Connect to DVDD to enable the BiSS/SSI interface.
The I/O pins A+, B+, Z+ are used for MA, SLO, SLI.

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Summary of Contents for iC-TW29

Page 1: ...LED intensity control by PWM output Low latency 2 4 µs or 5 0 µs Pin compatible with iC TW28 APPLICATIONS Rotary and linear incremental or absolute encoders Magnetic or optical sin cos sensor interface Brushless motor commutation 2 64 poles Imbedded motion control PACKAGES 32 pin QFN 5 mm x 5 mm x 0 9 mm RoHS compliant BLOCK DIAGRAM Interpolated Angle IA SPI Interface xSS SCK SO SI Interpolator ZE...

Page 2: ...in hosted applications In addition to industry standard incremental ABZ quadrature output the iC TW29 also provides UVW commutation output modes for 1 to 32 pole pair mo tors as well as BiSS and SPI interfaces The BiSS in terface provides BiSS encoder profiles 3 3S safety or 4 as well as optional electronic data sheet EDS SE functionality BiSS passthrough mode allows a host processor to implement ...

Page 3: ...terface 13 Encoder Link Interface 14 BiSS Interface 15 ADI Interface 16 FUNCTIONAL BLOCK DIAGRAM 17 ELECTRICAL CONNECTIONS 20 Power and Ground 22 Reference Outputs 22 xCALIB Input 22 SIN and COS Inputs 22 ZERO Inputs 23 ABZ Outputs 24 UVW Outputs 24 xRST Input 24 xIRQ 24 LED Output 24 BiSSEN Input 24 General Purpose I O 24 SPI Port 25 Reserved Pins 25 CONFIGURATION AND CALIBRATION 26 Introduction ...

Page 4: ...S422 Z Output or Multifunction I O 19 IOVSS I O Ground 20 B Differential RS422 B Output or Multifunction I O 21 B Differential RS422 B Output or Multifunction Output 22 IOVDD 3 3 V I O Power Supply Input 23 A Differential RS422 A Output or Multifunction I O 24 A Differential RS422 A Output or Multifunction I O 25 DVDD 3 3 V Digital Power Supply Input 26 LED4 LED Intensity Control Output or General...

Page 5: ...SS INTERFACE Rev C1 Page 5 28 PACKAGE DIMENSIONS 5 5 TOP 0 40 3 65 3 65 0 22 0 50 BOTTOM 0 90 0 10 SIDE R0 15 3 60 4 90 3 60 4 90 0 30 0 50 0 70 RECOMMENDED PCB FOOTPRINT drb_qfn32 5x5 6_pack_1 10 1 All dimensions given in mm Tolerances of form and position according to JEDEC MO 220 ...

Page 6: ...igured as push pull or open drain 17 Z Digital RS422 out Z or W Output In ABZ output modes these are the differential Z outputs In UVW output modes these are the W outputs In BiSS mode BISSEN pin high pin Z is the data input SLI If daisy chaining is not required Z can be grounded IOVSS In other modes these are multifunction I O 18 Z Digital RS422 out Z or W Output 19 IOVSS Ground I O Ground All gr...

Page 7: ... SI Digital in SPI Slave Input Connect to SPI master MO pin 30 SCLK Digital in SPI Slave Clock Input Connect to SPI master clock output pin 31 xSS Digital in SPI Slave Select Input Connects to SPI master slave select output pin 32 BISSEN Digital in BiSS Interface Enable Connect to DVDD to enable the BiSS SSI interface The I O pins A B Z are used for MA SLO SLI ...

Page 8: ... Referenced to DVSS AVSS and IOVSS 0 3 AVDD 0 3 V G003 Ipin Input Current into any pin 2 2 mA G004 Vesd1 ESD Susceptibility HBM 100 pF discharged through 1 5 kΩ 4 kV G005 Tj Junction Temperature 40 150 C THERMAL DATA Item Symbol Parameter Conditions Unit No Min Typ Max T01 Ta Operating Ambient Temperature Range 40 125 C T02 Rthja Thermal Resistance Chip to Ambient QFN32 5x5 surface mounted to PCB ...

Page 9: ...N 2 or COS COS 2 Refer to Figure 3 Minimum gain MAIN_CFG input 3 0 7 AVDD 1 45 V Maximum gain MAIN_CFG input 3 0 35 AVDD 1 1 V Minimum gain MAIN_CFG input 3 2 0 AVDD V Maximum gain MAIN_CFG input 3 1 0 AVDD V 104 fin Sin Cos Input Frequency 700 kHz 105 Vos Amplifier Input Offset Voltage 15 mV 106 Ilk Input Leakage Current 50 nA 108 OFFcorr Correctable Input Offset Voltage As percentage of input si...

Page 10: ... C 504 DRTraw Raw Data Retention Time 10 years 505 DRTact Actual Data Retention Time with error correction Tj 85 C 50 years Reset and Start Up xRST 601 DVDDonoff DVDD Power On Off Threshold xRST tied to DVDD 2 5 2 7 3 0 V 603 tstart Startup Time Valid EEPROM configuration START wait 0 2 ms Digital Input Pins xRST xCALIB A Encoder Link active A and B BiSS mode SI SCLK xSS GPIO BISSEN 701 Vt hi Inpu...

Page 11: ...e Output Current for continuous operation 15 mA A02 Vout hi Output Voltage High VDD 3 3 V Tj 27 C I 10 mA 2 7 V A03 Vs hi Saturation Voltage High Vs hi DVDD V LED I 10 mA 1 V A04 Vs lo Saturation Voltage Low I 10 mA 1 V A05 Isc hi Short Circuit Current High LED pin shorted to DVSS 40 mA A06 Isc lo Short Circuit Current Low LED pin shorted to DVDD 40 mA Bias Outputs VC VREF B01 VC Bias Voltage VC I...

Page 12: ...ferential Input Amplitude Ain diff Max SIN SIN or Max COS COS 0 V 1 85 V 0 7 V 2 2 V 0 35 V AVDD Minimum Gain Maximum Gain MAIN_CFG input 3 or MAIN_CFG zero 0 MAIN_CFG input 3 or MAIN_CFG zero 1 0 V 2 0 V 1 0 V AVDD Minimum Gain Maximum Gain Figure 3 Input Common Mode Range SIN SIN 2 COS COS 2 or ZERO ZERO 2 A B tMTD t whi T 100 AArel tAB ABrel Figure 4 Description of AB output signals 0 360 180 C...

Page 13: ...5 ns TEST spi 1 7 5 ns I003 tD2 Clock Signal Hi Level Duration TEST spi 0 15 ns TEST spi 1 7 5 ns I004 tS1 Setup Time xSS lo before SCLK lo hi 80 ns I005 tH1 Hold Time xSS lo after SCLK hi lo 50 ns I006 tW1 Wait Time between xSS lo hi and xSS hi lo 200 ns I007 tS2 Setup Time SI stable before SCLK lo hi 5 ns I008 tH2 Hold Time SI stable after SCLK lo hi 10 ns I009 tP1 Propagation Delay SO stable af...

Page 14: ...after activation I105 fclk A ELink Clock Frequency Signal driven into A 1 0 MHz I106 tD1 A ELink Clock Signal Hi Level Duration Signal driven into A 200 ns I107 tD2 A ELink Clock Signal Lo Level Duration Signal driven into A 200 ns I108 tS A ELink Input Setup Time Signal driven into A 200 ns I109 tH A ELink Input Hold Time Signal driven into A 200 ns I110 tP A ELink Output Propagation Delay Signal...

Page 15: ...500 ns I206 tP3 Output Propagation Delay 50 ns I207 tout Slave Timeout see Elec Char 809 BiSS C protocol BiSSEN pin high and BISS_CFG0 ssi 0 I208 tframe Permissible Frame Repetition indefinite I209 tC Permissible Clock Period 100 ns I210 tL1 Clock Signal Hi Level Duration 50 tout ns I211 tL2 Clock Signal Lo Level Duration 50 tout ns I212 tbusy Processing Time 240 ns I213 tP3 Output Propagation Del...

Page 16: ...ion Delay Variance not supported refer to tS and tH tC I307 tS Setup Time Data stable before clock edge lo hi without line delay compensation tP0 0 100 ns I308 tH Hold Time Data stable after clock edge lo hi without line delay compensation tP0 0 0 ns I309 tout Permissible Slave Timeout tC µs SSI Protocol ADI_CFG biss 0 I310 tframe Clock Frame Repetition Note This value can vary unpredictably durin...

Page 17: ...rent full absolute position of the iC TW29 The gearbox tracks the input cycles within a revolution and provides a normalized 26 bit output representing the angle within one output revolution NR This is synchronized with the revolution count RC and the cycle count CC from the absolute data interface ADI or SPI port to form the complete absolute position A programmable noise and jitter filter increa...

Page 18: ...n cos input signal quality The status fault monitor monitors 16 internal conditions each of which can be individually configured to activate a fault output to notify an external system during opera tion The fault output is the active low interrupt request output xIRQ pin In stand alone applications xIRQ can be used to directly drive a fault LED In hosted applications xIRQ is typically used to inte...

Page 19: ... as a chip ID and revision code In BiSS applica tions user programmable manufacturer ID product ID device serial number and production date are avail able The iC TW29 incorporates an internal write protected EEPROM to store configuration and initial calibration data for use at startup In addition to a standard check sum on the EEPROM data sophisticated data encoding allows detection and correction...

Page 20: ... components are required for operation Application Hint The input voltages must not exceed the chip s supply voltage 3 3 V VREF VC 100 nF 1µF AVDD AVSS 3 3V SIN SIN COS COS Sensor iC TW29 xSS SCLK SI SO SPI Configuration Port xCALIB Calibration Button 100 nF 1µF IOVDD 3 3V IOVSS A A B B Z Z 1µF DVDD DVSS 3 3V BISSEN ZERO ZERO xRST 3 3V xIRQ Fault LED Differential RS422 ABZ Outputs GPIO RESERVED RE...

Page 21: ...N ZERO ZERO xRST 3 3V xIRQ Fault LED BiSS Slave Interface GPIO RESERVED RESERVED 3 3V xSS SCLK MOSI MISO 3 3V iC HF X4 X3 X2 X6 X5 X1 CLK 120 Ω DATA DATA CLK Q4 NQ4 Q5 NQ5 Q2 NQ2 Q6 NQ6 Q3 NQ3 120 Ω 3 3V Regulator VDD VDDS 5V GND GNDS 0V MA SLI MA SLI 120 Ω 120 Ω 120 Ω SLO SLO MA A SLO B OEN FMSEL1 FMSEL2 Absolute Data Interface 5VS B1 B2 B3 A1 A2 A3 B4 A4 VCCB OE GND VCCA TXS0104E Figure 16 Typic...

Page 22: ...board voltage regulator Likewise the three ground pins can usually be connected to the same solid ground plane on the PC board If necessary separate voltage regulators can be used to power each section to provide enhanced noise immunity In all cases each power pin should have a dedicated 1µF decoupling capacitor placed as close to the iC TW29 as possible Reference Outputs The reference outputs VRE...

Page 23: ...ic systems a separate zero sensor is usually required Digital zero sensors Hall MR and others typically pro vide a single ended active low signal via an open drain output that pulls low in the presence of a magnetic field Connect active low open drain digital index sensors to the iC TW29 ZERO input and connect the ZERO in put to VDD 2 using a resistive voltage divider as shown in Figure 20 ZERO ZE...

Page 24: ...RST input is best controlled by the host For battery powered applications the host can hold xRST low to reduce power consumption low power mode See spec item 005 xIRQ In stand alone applications xIRQ functions as an ac tive low fault output It can be used to directly drive an LED with an appropriate current limiting resistor for fault indication In hosted applications xIRQ can be connected to an i...

Page 25: ...as shown in Figure 24 SO SI SCLK xSS xCS SCLK MO MI iC TW29 Host µP or µC 3 3V Figure 24 SPI Port Connection If the host processor or microcontroller can be discon nected the SPI port pins must be pulled up or down as shown in Figure 24 Do not allow any of the SPI port pins to float Although Figure 24 shows a single device application multiple iC TW29 s can also communicate over a single SPI chann...

Page 26: ...libration Once the iC TW29 is configured and calibrated the monitors and other advanced features can be enabled as needed Click on the EEPROM block in the block diagram on the main GUI window to open the EEPROM tab and save the default configuration to EEPROM Finally restart the iC TW29 by clicking the play button on the main GUI window Input Configuration and Calibration Click on the AFE IPO Anal...

Page 27: ...Haus approval in writing and precise reference to source The data specified is intended solely for the purpose of product description and shall represent the usual quality of the product In case the specifications contain obvious mistakes e g in writing or calculation iC Haus reserves the right to correct the specification and no liability arises insofar that the specification was from a third par...

Page 28: ...3 mm iC TW29 EVAL TW29_3D iC TW29 GUI Evaluation software for Windows PC entry of IC parameters file storage and transfer to DUT For download link refer to www ichaus com tw29 Please send your purchase orders to our order handling team Fax 49 0 61 35 92 92 692 E Mail dispo ichaus com For technical support information about prices and terms of delivery please contact iC Haus GmbH Tel 49 0 61 35 92 ...

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