IBT Technologies IB798, User Manual

Page: 37 / 56

BIOS SETUP
IB798 User’s Manual 33
Phoenix - AwardBIOS CMOS Setup Utility
CPU & PCI Bus Control
PCI Master 0 WS Write Enabled ITEM HELP
PCI Delay Transaction Enabled Menu Level
Vlink mode selection By Auto Menu Level
Vlink 8x Support Enabled
DRDY Timing Default
DRAM Clock / Drive Control
This field provides settings related to DRAM. The fields are listed
below.
Current FSB Frequency
The default setting of the FSB Frequency is 100MHz.
Current DRAM Frequency
The default setting of the DRAM Frequency is 266MHz.
DRAM Clock
The default setting of the DRAM clock is SPD.
DRAM Timing
This option refers to the method by which the DRAM timing is selected.
The default is Auto by SPD.
DRAM CAS Latency
This is the period between when the chipset requests data from memory
and when the memory is ready to send the data across the bus.
Bank Interleave
This decides how multiple memory modules communicate. It will only
make a difference if you have more than one memory module.
Precharge to Active(Trp)
Theamount of time from a bank precharge request to when it can be
activated.
Active to Precharge(Tras)
The Active to Precharge timing controls the length of the delay between
the activation and precharge commands – the length of time after
activation can the access cycle be started again.
Active to CMD(Trcd)
This is the time between a row access request and a column access
request.
REF to ACT/REF to REF(Trfc)
The default setting is 21T.
ACT(0) to ACT(1) (TRRD)
The default time setting is 4T.
DRAM Command Rate
The time to wait after a chip select before activate and read can be started.
Read to Precharge (Trtp)
The default time setting is 2T.