IBT Technologies IB798, User Manual

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BIOS SETUP
32 IB798 User’s Manual
Advanced Chipset Features
This Setup menu controls the configuration of the chipset.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Clock / Drive Control Press Enter ITEM HELP
AGP & P2P Bridge Control Press Enter Menu Level
CPU & PCI Bus Control Press Enter
Memory Hole Disabled
System BIOS Cacheable Enabled
Video RAM Cacheable Disabled
Init Display First PCI Slot
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Clock/Driver Control
Current FSB Frequency 100MHz ITEM HELP
Current DRAM Frequency 266MHz Menu Level
DRAM Clock By SPD
DRAM Timing Auto By SPD
DRAM CAS Latency 2.5/4
Bank Interleave Disabled
Precharge to Active (Trp) 4T
Active to Precharge (Tras) 7T
Active to CMD(Trcd) 4T
REF to ACT/REF to REF(Trfc) 21T
ACT(0) to ACT(1) TRRD) 3T
Read to Precharge (Trtp) 2T
Write to Read CMD (Twtr) 1T/2T
Write Recovery Time (Twr) 4T
DRAM Command Rate 2T Command
RDSAIT Mode Auto
RDSAIT Selection 03
Phoenix - AwardBIOS CMOS Setup Utility
AGP & P2P Bridge Control
AGP Aperture Size 128M ITEM HELP
AGP 3.0 Mode 8X
AGP Driving Control Auto Menu Level
AGP Driving Value DA
AGP Fast Write Disabled
AGP Master 1 WS Write Enabled
AGP Master 1 WS Read Enabled
AGP 3.0 Calibration cycle Disabled
VGA Share Memory Size 16M
Direct Frame Buffer Enabled
Outpost Port DIO
Dithering Disabled