IBT Technologies IB500, User Manual

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APPENDIX
IB500 User’s Manual 71
POST (hex) Description
47h Initialize EISA slot
49h
1. Calculate total memory by testing the last double word of each 64K page.
2. Program writes allocation for AMD K5 CPU.
4Eh
1. Program MTRR of M1 CPU
2. Initialize L2 cache for P6 class CPU & program CPU with proper
cacheable range.
3. Initialize the APIC for P6 class CPU.
4. On MP platform, adjust the cacheable range to smaller one in case the
cacheable ranges between each CPU are not identical.
50h Initialize USB
52h
Test all memory (clear all extended memory to 0)
55h Display number of processors (multi-processor platform)
57h
1. Display PnP logo
2. Early ISA PnP initialization
-Assign CSN to every ISA PnP device.
59h
Initialize the combined Trend Anti-Virus code.
5Bh
(Optional Feature)
Show message for entering AWDFLASH.EXE from FDD (optional)
5Dh 1. Initialize Init_Onboard_Super_IO switch.
2. Initialize Init_Onbaord_AUDIO switch.
60h Okay to enter Setup utility; i.e. not until this POST stage can users enter the
CMOS setup utility.
65h Initialize PS/2 Mouse
67h
Prepare memory size information for function call:
INT 15h ax=E820h
69h
Turn on L2 cache
6Bh Program chipset registers according to items described in Setup &
Auto-configuration table.
6Dh 1. Assign resources to all ISA PnP devices.
2. Auto assign ports to onboard COM ports if the corresponding item in Setup
is set to “AUTO”.
6Fh
1. Initialize floppy controller
2. Set up floppy related fields in 40:hardware.
73h (Optional Feature)
Enter AWDFLASH.EXE if :
-AWDFLASH is found in floppy drive.
-ALT+F2 is pressed
75h
Detect & install all IDE devices: HDD, LS120, ZIP, CDROM… ..
77h Detect serial ports & parallel ports.
7Ah
Detect & install co-processor