IBM TotalStorage 3534-F08, Installation And User Manual

Page: 27 / 105

CPU allows only direct control for DRAM, SRAM, ROM, and Flash memory, the
external CPLD controller is included to provide SDRAM controller functionality.
The I2C bus provides peripheral I/O control for the LEDs, the thermometers, and
general I/O functions. The 80960VH CPU serves as the master on the I2C bus.
The Bloom ASIC is an eight-port Fibre Channel switch controller. A proprietary
10-bit wide SSTL2 bus running at 106.25 MHz is used between the Bloom ASIC
and the SERDES.
Memory and memory architecture
The system design uses three types of memory devices:
v
DRAM
v
Flash File
v
Boot Flash
One on-board SDRAM chips provides up to 32 MB for system memory. One
additional SDRAM chip provides data parity. The printed circuit board (PCB)
SDRAM footprint is designed to be compatible with 64 MB, 128 MB, and 256 MB
devices. An external CPLD device added to the local bus provides control functions
for the 80960VH processor.
The system provides 4 MB of on-board redundant Flash File memory for software
and data storage. The Boot Flash is an 8-bit Flash device socket that is used only
for system start. The Boot Flash device contains a block area for startup code
protection. The PLCC32 socket supports 3.3 V Boot Flash memory up to 512 KB.
As with the 2019 series of switches and the 3534 1RU switch, the 3534 Model F08
is based on a central memory architecture. In this scheme, a set of buffers in the
central memory is assigned to each port to be used for receipt of frames. As an
ASIC port receives and validates a frame, it stores the frame in one of its receive
buffers in the central memory and forwards a routing request (a Put message) to
the appropriate destination ports. When a destination port is capable of transmitting
the frame, it reads the frame contents from central memory and forwards the frame
to its transmit interface. It does not wait for the frame to be written in memory,
unless the port is busy. After it has removed an entry for a frame from its internal
transmit queue in preparation for transmitting a frame, the destination port sends a
transmission complete message (a Finish message) to the port that received the
frame. This allows the receiving port to reuse the buffer for subsequent frames
received.
Central memory is also incorporated into the ASIC. Frames received on the ports in
an ASIC are written into the portion of central memory.
The ASIC contains a RAM device plus data path crossbar logic that is used to
implement the central memory. Memory blocks are accessed in a time-sliced
fashion. The buffer pool can be split into 2112-byte buffers or into 312-byte
mini-buffers. If frames that need to be buffered are smaller than the maximum 2112
bytes, using mini-buffers effectively expands the buffer pool and increases the
efficiency of memory usage by providing more (but smaller) receive buffers.
Additionally, the Bloom ASIC provides a special memory interface (SMI). The SMI
provides the firmware with a mechanism to read and write frame contents to and
from the ASIC. It also supports higher throughput transfers. The SMI includes a set
of two buffers that are large enough for an entire maximum-sized frame to be
Chapter 1. Introduction
5