IBM PC 100, Technical Manual

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Chapter 5. Bus Architecture
One ISA connector and the PCI connector directly below it share an expansion-slot opening at the back of
the computer that can be used by only one adapter at a time. This means that you can install either a
PCI adapter or an ISA adapter in a shared slot, but not both.
PCI devices receive data through the PCI controller. The PCI controller looks at all signals from the
microprocessor local bus, then passes them to the ISA controller or to peripherals connected to the PCI
bus.
The signal assignments and pin assignments for the PCI connectors are shown in Figure 16 on page 19.
For additional information, see the
PCI Local Bus Specification, published by the PCI Special Interest
Group.
Bus Voltage Levels
Four voltage levels are provided for I/O adapters. The maximum available values (for each slot) are as
follows:
Ÿ
+5 V dc (+5%,
−
4.5%) at 2.0 A
Ÿ
−
5 V dc (+10%,
−
9.5%) at 0.100 A
Ÿ
+12 V dc (+5%,
−
4.5%) at 0.175 A
Ÿ
−
12 V dc (+10%,
−
9.5%) at 0.100 A
The
I/O CH RDY
signal is available on the I/O channel to allow operation with slow I/O or memory devices.
I/O CH RDY
is held inactive by an addressed device to lengthen the operation. For each clock cycle that
the line is held inactive, one wait state is added to the I/O or DMA operation.
One voltage level is provided for PCI bus adapters. The maximum available values for each slot are +5 V
dc (+5%,
−
4.5%) at 7.576 A.
Chapter 5. Bus Architecture
39