IBM PC 100, Technical Manual

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Chapter 1. System Description
DMA I/O Address Map
Figure 4 (Page 3 of 3). I/O Address Map
Address (Hex) Device
B2E9–B6E7 Available I/O for ISA/PCI bus
B6E8 Cirrus GD5436
B6E9–BAE7 Available I/O for ISA/PCI bus
BAE8 Cirrus GD5436
BAE9–BEE7 Available I/O for ISA/PCI bus
BEE8 Cirrus GD5436
BEE9–E2E7 Available I/O for ISA/PCI bus
E2E8 Cirrus GD5436
E2E9 Available I/O for ISA/PCI bus
E2EA Cirrus GD5436
E2EB–FFFF Available I/O for ISA/PCI bus
Figure 5 (Page 1 of 2). DMA I/O Addresses for Memory Addresses, Word Counts, and Command/Status
Registers
Address (hex) Description Bits Byte Pointer
0000 Channel 0, Memory Address register 00–15 Yes
0001 Channel 0, Transfer Count register 00–15 Yes
0002 Channel 1, Memory Address register 00–15 Yes
0003 Channel 1, Transfer Count register 00–15 Yes
0004 Channel 2, Memory Address register 00–15 Yes
0005 Channel 2, Transfer Count register 00–15 Yes
0006 Channel 3, Memory Address register 00–15 Yes
0007 Channel 3, Transfer Count register 00–15 Yes
0008 Channels 0–3, Read Status/Write Command
register 00–07
0009 Channels 0–3, Write Request register 00–02
000A Channels 0–3, Write Single Mask register bits 00–02
000B Channels 0–3, Mode register (write) 00–07
000C Channels 0–3, Clear byte pointer (write) N/A
000D Channels 0–3, Master clear (write)/temp (read) 00–07
000E Channels 0–3, Clear Mask register (write) 00–03
000F Channels 0–3, Write All Mask register bits 00–03
0081 Channel 2, Page Table Address register
ñ
00–07
0082 Channel 3, Page Table Address register
ñ
00–07
0083 Channel 1, Page Table Address register
ñ
00–07
0087 Channel 0, Page Table Address register
ñ
00–07
0089 Channel 6, Page Table Address register
ñ
00–07
008A Channel 7, Page Table Address register
ñ
00–07
008B Channel 5, Page Table Address register
ñ
00–07
008F Channel 4, Page Table Address/Refresh register 00–07
00C0 Channel 4, Memory Address register 00–15 Yes
00C2 Channel 4, Transfer Count register 00–15 Yes
00C4 Channel 5, Memory Address register 00–15 Yes
00C6 Channel 5, Transfer Count register 00–15 Yes
00C8 Channel 6, Memory Address register 00–15 Yes
00CA Channel 6, Transfer Count register 00–15 Yes
00CC Channel 7, Memory Address register 00–15 Yes
00CE Channel 7, Transfer Count register 00–15 Yes
00D0 Channels 4–7, Read Status/Write Command
register 00–07
00D2 Channels 4–7, Write Request register 00–02
00D4 Channels 4–7, Write Single Mask register bit 00–02
00D6 Channels 4–7, Mode register (write) 00–07
00D8 Channels 4–7, Clear byte pointer (write) N/A
00DA Channels 4–7, Master clear (write)/temp (read) 00–07
00DC Channels 4–7, Clear Mask register (write) 00–03
00DE Channels 4–7, Write All Mask register bits 00–03
Chapter 1. System Description
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