IBM EM78P809N Specification Download | Manualshive

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EM78P809N

8-Bit Microcontroller

54

•

Product Specification (V1.0) 07.26.2005

(This specification is subject to change without further notice)

Voltage

Detector

Power-on

Reset

WDTE

Setup Time

VDD

D

Q

CLK

CLR

CLK

RESET

WDT Timeout

WDT

/RESET

Oscillator

Fig. 29.Controller Reset Block Diagram

4.15 Interrupt

The EM78P809N has 15 interrupts (9 external, 6 internal) listed below:

Table 9.. Interrupt Vector

Interrupt Source

Enable Condition

Int. Flag

Int. Vector Priority

Internal /

External

Reset -

-

0000

High

0

Internal WDT

WDTEN

WDTIF

0003

1

External

INT0

ENI + INT0EN=1

EXIEF0

0006

2

Internal

TCC

ENI + TCIE0=1

TCIF0

0009

3

External

INT1

ENI + EXIE1=1

EXIF1

000F

4

Internal

TBT

ENI + TBIE=1

TBIF

0012

5

External

UART Transmit

ENI + UTIE=1

TBEF

0015

6

External

UART Receive

ENI + URIE=1

TBFF

0018

7

External UART

Receive

error

ENI+UERRIE=1 UERRIF 001B

8

Internal

TC3

ENI + TCIE3=1

TCIF3

0021

9

External

SPI

ENI + SPIE=1

SPIF

0024

10

Internal

TC4

ENI + TCIE4=1

TCIF4

0027

11

External

INT3

ENI + EXIE3=1

EXIF3

002A

12

External

AD

ENI + ADIE=1

ADIF

0030

13

Internal

TC2

ENI + TCIE2=1

TCIF2

0033

14

External

INT5

ENI + EXIE5=1

EXIF5

0036

Low 15

ISFR0, ISFR1 and ISFR2 are the interrupt status registers that record the interrupt
requests in the relative flags/bits. IMR1 and IMR2 are the interrupt mask registers. The
global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.

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Summary of Contents for EM78P809N

Page 1: ...EM78P809N 8 BIT Microcontroller Product Specification DOC VERSION 1 0 ELAN MCCROELECTRONICS CORP July 2005...

Page 2: ...d or copied only in accordance with the terms of such agreement ELAN Microelectronics products are not intended for use in life support appliances devices or systems Use of ELAN Microelectronics produ...

Page 3: ...se Registers 23 4 4 CPU Operation Mode 27 4 5 AD Converter 29 4 6 Time Base Timer and Keytone Generator 31 4 7 UART Universal Asynchronous Receiver Transmitter 33 4 8 SPI Serial Peripheral Interface 3...

Page 4: ...Recommended Operating Conditions 63 6 Electrical Characteristics 64 6 1 DC Electrical Characteristics 64 6 2 AC Electrical Characteristic 67 6 3 Timing Diagram 68 APPENDIX 69 Package Types 69 Specifi...

Page 5: ...tage of ELAN Writer to easily program his development code 2 Features 2 1 CPU Operating voltage 2 5V 5 5V Operating temperature range 40 C 85 C Operating frequency range base on 2 clocks z Crystal mod...

Page 6: ...ace z Serial Peripheral Interface SPI Three wire synchronous communication z Universal asynchronous receiver transmitter interface UART Two wire asynchronous communication AD converter z 8 channel 10...

Page 7: ...or crystal oscillator RC type Instruction clock output External clock signal input RESET 27 I Input pin with Schmitt trigger If this pin remains at logic low the controller will also remain in reset c...

Page 8: ...le divider output PDO P80 P81 can be used as pull high or pull low pins P90 P97 4 11 I O P90 P97 are bi directional I O pins P90 P97 can be used as 8 channel 10 bit resolution A D converter P97 can be...

Page 9: ...ROL BUS General RAM R4 R1 TCC Interrupt Control Instruction Register Instruction Decoder ROM Stack R2 ALU ACC R3 R5 OSCI OSCO PORT6 IOC6 R6 PORT7 IOC7 R7 PORT8 IOC8 R8 PORT9 IOC9 R9 TC 2 16 bit Timer...

Page 10: ...R ADDL TC2DH TC2DL ADCR ADIC ADDH TBKTC Reserved URC1 URC2 URS URRD URTD Reserved Reserved Reserved Reserved Reserved Reserved SPIC1 SPIC2 SPID Reserved Reserved Reserved PHC1 PLC1 PHC2 PLC2 Reserved...

Page 11: ...enerates 8192 13 bits on chip OTP ROM addresses to the relative programming instruction codes One program page is 1024 words long R2 is set as all 0 s when under RESET condition JMP instruction allows...

Page 12: ...in Interrupt Occurs 0009h UART Transmit Data Buffer Empty UART Receive Data Buffer Full 000Fh 0015h 0018h UART Receive Error 001Bh TC3 Interrupt 0021h SPI Interrupt 0024h TC4 Interrupt 0027h External...

Page 13: ...RSR5 RSR0 are used to select the registers address 00h 3Fh in the indirect addressing mode If no indirect addressing is used the RSR can be used as an 8 bit general purpose read write register See the...

Page 14: ...put H level release PORT6 Port 6 I O Data Register Address 06h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P67 P66 P65 P64 P63 P62 P61 P60 Bit 7 Bit 0 P67 P60 8 bits Port 6 I O data register User...

Page 15: ...Bit 7 Bit 6 TC4FF1 TC4FF0 Timer Counter4 flip flop control TC4FF1 TC4FF0 Operating Mode 0 0 Clear 0 1 Toggle 1 0 Set 1 1 Reserved Bit 5 TC4S Timer Counter 4 start control TC4S 0 Stop and clear counter...

Page 16: ...ed by software Bit 0 EXIF0 External interrupt flag INT0 Flag cleared by software If the INT0EN is reset to 0 the flag is cleared ISFR1 Interrupt Status Flag Register 1 Address 0Eh Bit 7 Bit 6 Bit 5 Bi...

Page 17: ...er Interrupt Flag Flag cleared by software Bit 2 EXIF1 External Interrupt Flag INT1 Flag cleared by software Bit 0 TCIF0 TCC Overflow Interrupt Flag Set as TCC overflows flag cleared by software 1 mea...

Page 18: ...C3DA4 TC3DA3 TC3DA2 TC3DA1 TC3DA0 Bit 7 Bit 0 TC3DA7 TC3DA0 Data buffer of 8 bit Timer Counter 3 Reset does not affect this register TC3DB Timer 3 Data Buffer B Address 07h Bit 7 Bit 6 Bit 5 Bit 4 Bit...

Page 19: ...D13 TC2D12 TC2D11 TC2D10 TC2D9 TC2D8 Bit 7 Bit 0 TC2D15 TC2D8 16 bit Timer Counter 2 data buffer high byte TC2DL Timer 2 Data Buffer Low Byte Address 0Ah Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit...

Page 20: ...0 ADIS2 ADIS0 Analog Input Pin Select ADIS2 ADIS1 ADIS0 Analog Input Pin 0 0 0 AD0 0 0 1 AD1 0 1 0 AD2 0 1 1 AD3 1 0 0 AD4 1 0 1 AD5 1 1 0 AD6 1 1 1 AD7 ADIC AD Input Pin Control Address 0Ch Bit 7 Bit...

Page 21: ...76kHz 0 1 Fc 2 12 1 953kHz 1 0 Fc 2 11 3 906kHz 1 1 Fc 2 10 7 812kHz Bit 3 TBTEN Time Base Timer Enable Control TBTEN 0 Disable TBTEN 1 Enable Bit 2 Bit 0 TBTCK2 TBTCK0 Time Base Timer Clock Source Se...

Page 22: ...1 when transfer buffer is empty Reset to 0 automatically when writing into the URTD register UTBE bit will be cleared by hardware when enabling the transmission UTBE bit is read only Therefore writin...

Page 23: ...ERR Overrun error flag Set to 1 when overrun error occurred and cleared to 0 by software Bit 2 FMERR Framing error flag Set to 1 when framing error occurred and cleared to 0 by software Bit 1 URBF UAR...

Page 24: ...dle of data output time SMP 1 Input data sampled at the end of data output time In using external clock data input sample is fixed at the middle of data output time Bit 6 DCOL SPI Data collision DCOL...

Page 25: ...M0 SPI Transfer Mode Select TC2CK1 TC2CK0 Transfer Mode 0 0 8 bit Transmit Receive mode 0 1 8 bit Transmit mode 1 0 8 bit Receive mode 1 1 Reserved Bit 0 RBF Set to 1 by Buffer Full Detector and clear...

Page 26: ...E8x 1 Disable P8x pull low Bit 3 0 PLE63 PLE60 bits 3 0 of Port 6 Pull low enable bit PLE6x 0 Enable P6x pull low PLE6x 1 Disable P6x pull low PHC2 Pull High Control Register 2 Address 0Ch Bit 7 Bit 6...

Page 27: ...PSR0 CONT register is both readable and writable Bit 7 WDTO WDT output select WDTO 0 Interrupt request WDTO 1 Internal reset Bit 6 INT Interrupt enable flag INT 0 masked by DISI or hardware interrupt...

Page 28: ...2 Bit 1 Bit 0 INT1NR INT0EN 0 INT3ES1 INT3ES0 0 INT1ES TC2ES Bit 7 INT1NR INT1 noise reject time select INT1NR 0 Pulses less than 63 fc are eliminated as noise INT1NR 1 Pulses less than 15 fc are elim...

Page 29: ...F 2 VOF 1 VOF 0 0 0 0 Bit 7 CALI Calibration enable bit for A D offset CALI 0 Calibration disable CALI 1 Calibration enable Bit 6 SIGN Polarity bit of offset voltage SIGN 0 Negative voltage SIGN 1 Pos...

Page 30: ...nterrupt TCIE3 1 enable TCIF3 interrupt Individual interrupt is enabled by setting its associated control bit in the IMR1 to 1 Global interrupt is enabled by the ENI instruction and is disabled by the...

Page 31: ...idual interrupt is enabled by setting its associated control bit in the IMR2 to 1 Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction IMR2 register is both reada...

Page 32: ...shed If the ENI instruction is not set the next instruction will be executed which is after the IDLE mode start instruction IDLE mode can also be released by setting the RESET pin to low and executing...

Page 33: ...care Interrupt request flag will be recorded 4 5 AD Converter Registers for AD Converter Circuit R_BANK Address NAME Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BANK 1 0X0B ADCR ADREF ADRUN ADCK1...

Page 34: ...ccuracy linearity and speed of the successive approximation A D converter are dependent on the properties of the ADC The source impedance and the internal sampling impedance directly affect the time r...

Page 35: ...BANK Address NAME Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BANK 1 0X0E TBKTC TEN TCK1 TCK0 0 TBTEN TBTCK2 TBTCK1 TBTCK0 R W R W R W R W R W R W R W BANK 0 0x0F ISFR2 0 UERRIF RBFF TBEF TBIF EXI...

Page 36: ...Fosc 2 Fosc 2 Fosc 2 Fosc 2 Fosc 2 Fosc 2 23 21 16 14 13 12 11 9 TBKTC TBTCK2 0 3 Falling Edge Detector TBT Interrupt TBTEN Fig 9 TBT Configuration Time Base Timer is used to generate the base time fo...

Page 37: ...W R W BANK 2 0X07 URS URRD8 EVEN PRE PRERR OVERR FMERR URBF RXE R W R W R W R W R W R W R R W BANK 2 0X08 URRD URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0 R R R R R R R R BANK 2 0X09 URTD URTD 7 U...

Page 38: ...followed by the data bits in which the least significant bit LSB comes first The data bits are followed by the parity bit If present then the stop bit or bits high confirm the end of the frame In rec...

Page 39: ...RXE bit of the URS register to enable the UART receiving function The UART monitors the RX pin and synchronizes internally when it detects a start bit 2 Receive data is shifted into the URRD register...

Page 40: ...1 Bit 0 BANK 3 0X05 SPIC1 SMP DCOL BRS2 BRS1 BRS0 EDS DORD WBE R W R W R W R W R W R W R W R BANK 3 0X06 SPIC2 SPIS 0 0 0 0 SPIM1 SPIM0 RBF R W R W R W R BANK 3 0X07 SPID SPID7 SPID6 SPID5 SPID4 SPID3...

Page 41: ...dge or falling edge and latch the data Setting up the SMP bit of the SPIC2 register can select the sample phase at the middle or at the end of the data output time 4 8 3 Transfer Mode The transmit rec...

Page 42: ...pin a0 a1 a2 a3 a4 a5 a6 a7 a SPID b0 b1 b2 b3 b4 b5 b6 b7 read data b shift finish Fig 16 Receive Mode 8 bit 1 word c 8 bit Transmit Receive Mode Set SPIM0 SPIM1 to transmit receive mode and write da...

Page 43: ...eive Mode 8 bit 1 word d Multiple Device Connect SS When selecting external clock for transfer clock source the SS function can be used This pin SS will be active when the SS function is enabled else...

Page 44: ...TC2D11 TC2D10 TC2D9 TC2D8 R W R W R W R W R W R W R W R W BANK 1 0X0A TC2DL TC2D7 TC2D6 TC2D5 TC2D4 TC2D3 TC2D2 TC2D1 TC2D0 R W R W R W R W R W R W R W R W BANK 0 0x0E ISFR1 EXIF5 TCIF2 ADIF 0 EXIF3 T...

Page 45: ...TC2 pin and either rising or falling can be selected by setting TC2ES When the contents of the up counter matched with the TCR2 TCR2H TCR2L then interrupt is generated and the counter is cleared Coun...

Page 46: ...4 Bit 3 Bit 2 Bit 1 Bit 0 BANK 1 0X05 TC3CR TC3CAP TC3S TC3CK1 TC3CK0 TC3M 0 0 0 R W R W R W R W R W BANK 1 0X06 TC3DA TC3DA7 TC3DA6 TC3DA5 TC3DA4 TC3DA3 TC3DA2 TC3DA1 TC3DA0 R W R W R W R W R W R W...

Page 47: ...using the external clock input pin TC3 pin and either rising or falling edge can be selected by INT3ES0 but both edge cannot be used When the contents of the up counter matched with the TCR3DA then i...

Page 48: ...d until TCR3DA is read out K 2 K 1 K 0 1 m 1 m m 1 n 1 n 0 1 2 3 FE FF0 1 2 3 Source Clock Up counter TC3 Pin Input TCR3DA TCR3DB TC3 Interrupt Reading TCR3DA K m n FF Overflow FE Capture Capture Over...

Page 49: ...med on the rising edge of the external clock input pin TC4 pin When the contents of the up counter matched with the TCR4 then interrupt is generated and the counter is cleared Counting up resumes afte...

Page 50: ...CR4 TC4 Interrupt n n n 2 F F PWM Match Overflow n 1 n Match n 2 Overflow 1 Period n m m m Overwrite Shift m 1 1 m Fig 27 Timing Chart for PWM Mode 4 12 TCC WDT Prescaler An 8 bit counter is available...

Page 51: ...1 M U X IOD PCRD Fig 28 The I O Port and I O Control Register Circuit 4 14 RESET and Wake up 4 14 1 RESET A RESET is initiated by one of the following events 1 Power on reset 2 RESET pin input low 3 W...

Page 52: ...he controller will be waken up and execute the next instruction after entering SLEEP mode All the registers will maintain their original values before SLEP instruction was executed 2 RESET pin pull lo...

Page 53: ...time out 0 P P P P U U U 0x0C ADOSC R Wake Up from SLEEP IDLE mode 0 P P P P U U U Bit Name EXIE5 TCIE2 ADIE X EXIE3 TCIE4 SPIE TCIE3 Power on 0 0 0 U 0 0 0 0 RESET and WDT time out 0 0 0 U 0 0 0 0 0...

Page 54: ...U U U U P P Bit Name P97 P96 P95 P94 P93 P92 P91 P90 Power On 1 1 1 1 1 1 1 1 RESET and WDT time out 1 1 1 1 1 1 1 1 0x09 PORT9 Wake Up from SLEEP IDLE mode P P P P P P P P Bit Name TC4FF1 TC4FF0 TC4S...

Page 55: ...DDL Wake Up from SLEEP IDLE mode P P U P 0 P P P Bit Name TC2D15 TC2D14 TC2D13 TC2D12 TC2D11 TC2D10 TC2D9 TC2D8 Power On 0 0 0 0 0 0 0 0 RESET and WDT time out 0 0 0 0 0 0 0 0 0x09 TC2DH Wake Up from...

Page 56: ...P P P P P P P P Register Bank 3 Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name SMP DCOL BRS2 BRS1 BRS0 EDS DORD WBE Power On 0 0 0 0 0 0 0 0 RESET and WDT time out P...

Page 57: ...The Status of RST T and P of STATUS Register The values of T and P are used to verify the event that triggered the processor to wake up Table 7 shows the events that may affect the status of T and P T...

Page 58: ...TCIE0 1 TCIF0 0009 3 External INT1 ENI EXIE1 1 EXIF1 000F 4 Internal TBT ENI TBIE 1 TBIF 0012 5 External UART Transmit ENI UTIE 1 TBEF 0015 6 External UART Receive ENI URIE 1 TBFF 0018 7 External UAR...

Page 59: ...External RC oscillator mode ERC oscillator mode User can select which mode by Code Option Register The maximum limit for operational frequencies of the crystal resonator under different VDDs is liste...

Page 60: ...S OSCI OSCO EM78P809N Fig 31 Crystal Resonator Circuit Table12 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator Oscillator Type Frequency Mode Frequency C1 pF C2 pF 2 0 MHz 20 40...

Page 61: ...uency also varies slightly from one chip to another due to the manufacturing process variation In order to maintain a stable system frequency the values of the Cext should not be less than 20pF and th...

Page 62: ...2 For design reference only 4 17 Code Option Register The EM78P809N has one CODE option word that is not part of the normal program memory The option bits cannot be accessed during normal program exe...

Page 63: ...it 0 XXXXXXXXXXXXX Bits 12 0 Customer s ID code 4 18 Power on Considerations Any microcontroller is not guaranteed to start and operate properly before the power supply maintains at its steady state T...

Page 64: ...idly and fully Rin the current limited resistor will prevent high current or ESD electrostatic discharge from flowing to pin RESET EM78P809N RESET Vdd D R Rin C Fig 35 External Power Up Reset Circuit...

Page 65: ...cles JMP CALL RET RETL RETI including the conditional skip JBS JBC JZ JZA DJZ DJZA instructions In addition instructions that are written to the program counter are executed within two instruction cyc...

Page 66: ...rr 02rr OR R A A R R Z 0 0010 10rr rrrr 02rr AND A R A R A Z 0 0010 11rr rrrr 02rr AND R A A R R Z 0 0011 00rr rrrr 03rr XOR A R A R A Z 0 0011 01rr rrrr 03rr XOR R A A R R Z 0 0011 10rr rrrr 03rr ADD...

Page 67: ...11 kkkk kkkk 1Fkk ADD A k k A A Z C DC 1 1110 1000 kkkk 1E8k PAGE k K R5 6 4 None 1 1110 1001 kkkk 1E9k BANK k K R4 7 6 None Note1 This instruction is applicable to IOC6 IOCA IMR1 IMR2 only 5 Absolute...

Page 68: ...D V VIHT1 Input High Threshold Voltage Schmitt trigger RESET TCC INT 0 7 VDD VDD 0 3V V VILT1 Input Low Threshold Voltage Schmitt trigger RESET TCC INT 0 3V 0 3 VDD V VIHX1 Clock Input High Voltage OS...

Page 69: ...ge Schmitt trigger RESET TCC 0 7 VDD VDD 0 3V V VILT2 Input Low Threshold Voltage Schmitt trigger RESET TCC 0 3V 0 3 VDD V VIHX1 Clock Input High Voltage LOSCI OSCI in crystal mode 0 7 VDD VDD 0 3V V...

Page 70: ...rrent VDD VAREF 5 0V VASS 0 0V V reference from VREF 200 250 300 uA RN Resolution VDD VAREF 5 0V VASS 0 0V 9 10 Bits LN Linearity error VDD 2 5 to 5 5V Ta 25 0 1 2 LSB DNL Differential nonlinear error...

Page 71: ...2000 ns Twdt Watchdog timer period Ta 25 C 11 3 16 2 21 6 ms Tset Input pin setup time 0 ns Thold Input pin hold time 20 ns Tdelay Output pin delay time Cload 20pF 50 ns Tstup1 SDI data setup time Se...

Page 72: ...tice 6 3 Timing Diagram RESET Timing CLK 0 CLK RESET NOP Instruction 1 Executed Tdrh TCC Input Timing CLKS 0 CLK TCC Ttcc Tins AC Testing Input is driven at 2 4V for logic 1 and 0 4V for logic 0 Timin...

Page 73: ...pecification V1 0 07 26 2005 69 This specification is subject to change without further notice APPENDIX Package Types OTP MCU Package Type Pin Count Package Size EM78P809NP DIP 28 600 mil EM78P809NM S...

Page 74: ...Base Timer and Keytone Generator 31 4 7 UART Universal Asynchronous Receiver Transmitter 33 4 8 SPI Serial Peripheral Interface 36 4 9 Timer Counter 2 40 4 10 Timer Counter 3 42 4 11 Timer Counter 4...

Page 75: ...EM78P809N 8 Bit Microcontroller Product Specification V1 0 07 26 2005 71 This specification is subject to change without further notice APPENDIX 69 Package Types 69...

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