IBM Deskstar 120 GXP Page 188 Specifications Download

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11.33.4.4 Error log data structure

Data format of error data structure is shown below.

3Ch

Error data structure

30h

5th command data structure

24h

4th command data structure

18h

3rd command data structure

0Ch

2nd command data structure

00h

1st command data structure

Offset

Byte

Description

Figure 147. Error log data structure

Command data structure
Data format of each command data structure is shown below.

08h

Time stamp (ms from Power On)

07h

Command register

06h

Device/Head register

05h

Cylinder High register

04h

Cylinder Low register

03h

Sector number register

02h

Sector count register

01h

Features register

00h

Device Control register

Offset

Byte

Description

Figure 148. Command data structure

Deskstar 120GXP hard disk drive specifications

174

Summary of Contents for Deskstar 120 GXP

Page 1: ...XP 3 5 inch Ultra ATA 100 hard disk drive IC35L020AVVN07 IC35L040AVVN07 IC35L060AVVA07 IC35L080AVVA07 IC35L100AVVA07 IC35L120AVVA07 Models Revision 4 1 18 June 2002 S07N 4778 08 Publication 2820 IBM s...

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Page 3: ...XP 3 5 inch Ultra ATA 100 hard disk drive IC35L020AVVN07 IC35L040AVVN07 IC35L060AVVA07 IC35L080AVVA07 IC35L100AVVA07 IC35L120AVVA07 Models Revision 4 1 18 June 2002 S07N 4778 08 Publication 2820 IBM s...

Page 4: ...typographical errors Changes are periodically made to the information herein these changes will be incorporated in new editions of the publication IBM may make improve ments or changes in any product...

Page 5: ...al interface 21 6 0 Specification 19 5 0 Defect flagging strategy 18 4 4 6 Operating modes 17 4 4 5 Throughput 16 4 4 4 Data transfer speed 15 4 4 3 Drive ready time 13 4 4 2 Mechanical positioning 13...

Page 6: ...andard conformity 60 6 11 Safety 59 6 10 Identification labels 58 6 9 Acoustics 57 6 8 5 Rotational shock 56 6 8 4 Nonoperating shock 56 6 8 3 Operating shock 55 6 8 2 Nonoperating vibration 55 6 8 1...

Page 7: ...otected Area Function 86 9 8 5 Command table 83 9 8 4 Operation example 82 9 8 3 Passwords 82 9 8 2 Security level 82 9 8 1 Security mode 82 9 8 Security Mode Feature Set 81 9 7 8 Self test 80 9 7 7 E...

Page 8: ...6 11 24 Security Freeze Lock F5h 144 11 23 Security Erase Unit F4h 143 11 22 Security Erase Prepare F3h 142 11 21 Security Disable Password F6h 141 11 20 Recalibrate 1xh 139 11 19 Read Verify Sectors...

Page 9: ...190 11 41 Write Sectors 30h 31h 188 11 40 Write Multiple C5h 186 11 39 Write Long 32h 33h 184 11 38 Write DMA Queued CCh 182 11 37 Write DMA CAh CBh 181 11 36 Write Buffer E8h Deskstar 120GXP hard dis...

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Page 11: ...Ultra DMA cycle timing chart Host terminating Read 31 Figure 30 Ultra DMA cycle timings Host pausing Read 31 Figure 29 Ultra DMA cycle timing chart Host pausing Read 30 Figure 28 Ultra DMA cycle timi...

Page 12: ...s 75 Figure 78 Reset error register values 74 Figure 77 Diagnostic Codes 74 Figure 76 Default Register Values 73 Figure 75 Reset Response Table 72 Figure 74 Status Register 70 Figure 73 Error Register...

Page 13: ...Set Features Command EFh 152 Figure 130 Service Command A2h 151 Figure 129 Seek Command 7xh 150 Figure 128 Security Unlock Information 149 Figure 127 Security Unlock Command F2h 148 Figure 126 Securit...

Page 14: ...193 Figure 160 Time out values 190 Figure 159 Write Sectors Command 30h 31h 188 Figure 158 Write Multiple Command C5h Deskstar 120GXP hard disk drive specifications xii...

Page 15: ...ischarge Kbpi 1 000 bits per inch Ktpi 1 000 tracks per inch Mbps 1 000 000 bits per second GB 1 000 000 000 bytes MB 1 000 000 bytes KB 1 000 bytes unless otherwise specified 32KB 32 x 1024 bytes 64K...

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Page 17: ...f 2048 KB Upper 184 5 KB is used for firmware Ring buffer implementation Write Cache Queued feature support Advanced ECC On The Fly EOF Automatic Error Recovery procedures for read and write commands...

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Page 19: ...Part 1 Functional specification Deskstar 120GXP hard disk drive specifications 5...

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Page 21: ...n if an error occurs Monitors various timers such as head settle and servo failure Performs self checkout diagnostics 3 2 Head disk assembly The head disk assembly HDA is assembled in a clean room env...

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Page 23: ...20 5 Label capacity GB Physical Layout IC35L060AVVA07 IC35L040AVVN07 IC35L020AVVN07 Description 123 522 416 640 102 935 347 200 82 348 277 760 Total Logical Data Bytes 241 254 720 201 045 600 160 836...

Page 24: ...2 Data sheet 31 31 Number of data bands 29 7 29 7 Areal density max Gbits in2 54 56 7 Track density Ktpi 547 524 Recording density max Kbpi up to 56 up to 56 Number of buffer segments write up to 12...

Page 25: ...10 34784 18 740 698 29580 31269 31235 33009 17 768 725 27930 29579 29502 31234 16 768 740 26170 27929 27653 29501 15 792 752 24620 26169 26025 27652 14 806 768 22920 24619 24139 26024 13 822 787 21220...

Page 26: ...which can be sent and retrieved via read write commands and a spare area for reassigned data Spare cylinder The spare cylinder is used by IBM manufacturing and includes data sent from a defect locatio...

Page 27: ...of DRQ for the first data byte of a READ command when the requested data is not in the buffer excluding Physical seek time and Latency The table below gives average command overhead not applicable 0 3...

Page 28: ...re max maximum seek length n seek length 1 to max Tnin inward measured seek time for an n track seek Tnout outward measured seek time for an n track seek 4 4 2 2 Full stroke seek without command overh...

Page 29: ...le track seek is measured as the average of one 1 single track seek from every track with a random head switch in both directions inward and outward 4 4 2 6 Average latency 4 17 8 3 7200 RPM Average l...

Page 30: ...linear density recording Sustained disk buffer transfer rate Mbyte sec is defined by considering head cylinder change time for read operation This gives a local average data transfer rate It is deriv...

Page 31: ...d data rate T A B C 16 777 216 D 512 E READ where T Calculated time sec A Command process time Command overhead sec B Average seek time sec C Average latency sec D Sustained disk buffer transfer rate...

Page 32: ...Only soft reset or hard reset can change the mode to standby Note Upon power down or spindle stop a head locking mechanism will secure the heads in the OD park ing position 4 4 6 2 Mode transition tim...

Page 33: ...eas are optimally used No extra sector is wasted as a spare throughout user data areas All pushes generated by defects are absorbed by the spare tracks of the inner zone N N 1 N 2 N 3 defect defect sk...

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Page 35: ...he DC power connector is designed to mate with AMP part number 1 480424 0 using AMP pins part number 350078 4 strip part number 61173 4 loose piece or their equivalents Pin assignments are shown in th...

Page 36: ...le of signals Notes 1 O designates an output from the drive 2 I designates an input to the drive 3 I O designates an input output common 4 OC designates open collector or open drain output 5 The signa...

Page 37: ...data register has been addressed and that the drive is prepared to send or receive a 16 bit wide data word This signal is an Open drain output with 24 mA sink capability and an external resistor is ne...

Page 38: ...o 5 V through a 15 K resistor The tolerance of the resistor value is 50 to 100 DMARQ This signal used for DMA data transfers between host and drive shall be asserted by the drive when it is ready to t...

Page 39: ...ignal from the device for an Ultra DMA data in transfer Both the rising and falling edge of DSTROBE latch the data from DD 15 0 into the host The device may stop toggling DSTROBE to pause an Ultra DMA...

Page 40: ...ve reset timing t10 t14 RESET BUSY Figure 21 System reset timing chart 31 RESET high to not BUSY t14 25 RESET low width t10 Max sec Min sec PARAMETER DESCRIPTION Figure 22 System reset timing Deskstar...

Page 41: ...lse width tB 35 IORDY set up time tA 10 DIOR DIOW to address valid hold t9 30 Address invalid to IOCS16 negation t8 40 Address valid to IOCS16 assertion t7 5 DIOR data hold t6 20 DIOR data setup t5 10...

Page 42: ...iple operations the interval from the end of negation of the DRQ bit until setting of the next DRQ bit is as follows In the event that a host reads the status register only before the sector or block...

Page 43: ...eleased tZ 10 CS 1 0 hold tN 25 CS 1 0 valid to DIOR DIOW tM 35 DIOR DIOW to DMARQ delay tLR tLW 25 DIOR DIOW negated pulse width tKR tKW 5 DIOR DIOW to DMACK hold tJ 0 DMACK to DIOR DIOW setup tI 10...

Page 44: ...ost tDH 4 5 7 7 10 15 Data setup time at host tDS 0 0 0 0 0 0 Maximum time allowed for output drivers to assert tZAD 10 10 10 10 10 10 Maximum time allowed for output drivers to release tAZ 38 57 86 1...

Page 45: ...20 30 50 DSTROBE to HDMARDY time tSR MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MODE5 MODE4 MODE3 MODE2 MODE1 MODE0 PARAMETER DESCRIPTION all values in ns Note When a host does not satisfy tSR ti...

Page 46: ...5 7 7 10 15 CRC word setup time at device side tCS 20 20 20 20 20 20 Interlocking time with minimum tMLI 20 20 20 20 20 20 Minimum delay time required for output tZAH 10 10 10 10 10 10 Maximum time a...

Page 47: ...vice side tCH 5 5 7 7 10 15 CRC word setup time at device side tCS 20 20 20 20 20 20 Interlock time with minimum tMLI 20 20 20 20 20 20 Minimum delay time required for output tZAH 10 10 10 10 10 10 Ma...

Page 48: ...tDS 38 57 86 115 154 230 Two Cycle time t2CYC 16 8 25 39 54 73 112 Cycle time tCYC 75 0 100 0 100 0 150 0 150 0 150 0 Limited interlock time tLI 0 0 0 0 0 0 Minimum time before driving IORDY tZIORDY 5...

Page 49: ...0 50 HSTROBE to DDMARDY response time tSR MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MODE5 MODE4 MODE3 MODE2 MODE1 MODE0 PARAMETER DESCRIPTION all values in ns Note When a device does not satisfy...

Page 50: ...ACK tACK 5 5 5 5 5 5 CRC word hold time at device side tCH 5 5 7 7 10 15 CRC word setup time at device side tCS 20 20 20 20 20 20 Interlock time with minimum tMLI 75 0 100 0 100 0 150 0 150 0 150 0 Li...

Page 51: ...old time for DMACK tACK 5 5 5 5 5 5 CRC word hold time at device side tCH 5 5 7 7 10 15 CRC word setup time at device side tCS 20 20 20 20 20 20 Interlock time with minimum tMLI 75 0 100 0 100 0 150 0...

Page 52: ...Sector count Reg Sector count Reg 0 1 0 1 0 Features Reg Error Reg 1 0 0 1 0 Data Reg Data Reg 0 0 0 1 0 Command Block Registers DIOW 0 Write DIOR 0 Read DA0 DA1 DA2 CS1 CS0 Figure 43 I O address map...

Page 53: ...on Jumper pins Figure 44 Jumper pin location 2 and 3 disk model shown 6 3 2 Jumper pin identification Pin A Pin B Pin I DERA001 prz Figure 45 Jumper pin identification 2 and 3 disk model shown Desksta...

Page 54: ...e Selection or Device 1 Slave Present as shown in the following figures The Device 0 setting automatically recognizes device 1 if it is present The Device 1 Slave Present setting is for a slave device...

Page 55: ...ions for normal use Notes 1 To enable the CSEL mode Cable Selection mode the jumper block must be installed at E F In the CSEL mode the drive address is determined by AT interface signal 28 CSEL as fo...

Page 56: ...mper positions for 15 logical head default Notes 1 To enable the CSEL mode Cable Selection mode the jumper block must be installed at E F In the CSEL mode the drive address is determined by AT interfa...

Page 57: ...DEVICE1 Slave Present Figure 49 Jumper positions for capacity clip to 2GB 32GB Notes For the 20 GB model factory default capacities less than 32GB The jumper setting acts as a 2GB clip which clips th...

Page 58: ...o Spin Notes 1 These jumper settings are used for limiting power supply current when multiple drives are used 2 Command to spin up is SET FEATURES subcommand 07h Refer to 12 28 Set Features 3 To enabl...

Page 59: ...m Temperature Relative humidity Maximum wet bulb temperature Maximum temperature gradient Altitude Operating conditions Figure 51 Temperature and humidity Notes 1 The system is responsible for provid...

Page 60: ...65C 14 Nonoperating Operating Figure 52 Limits of temperature and humidity Note Storage temperature range is 0 to 65 6 4 2 Corrosion test The drive shows no sign of corrosion inside and outside of the...

Page 61: ...cations 6 5 2 Power supply current typical 0 9 1 15 3 150 Sleep average 1 0 1 15 3 160 Standby average 86 1867 20 740 Start up max 46 820 22 790 Silent R W peak 8 0 36 470 10 470 Silent R W average 1...

Page 62: ...B and 60 GB models 0 9 1 15 6 139 Sleep average 1 0 1 15 3 156 Standby average 15 1700 25 713 Start up max 6 705 43 738 Silent R W peak 6 5 31 350 12 459 Silent R W average 29 1520 43 738 Random R W p...

Page 63: ...he dynamic loading of the other drives must remain within the above regulation tolerance A common supply with separate power leads to each drive is a more desirable method of power distribution To pre...

Page 64: ...n a 40 C environment and a minimum of 10 000 start stop cycles in extreme temperature or humidity within the operating range See Figure 51 on page 45 and Figure 52 on page 46 6 6 4 Preventive maintena...

Page 65: ...OLE Dia 2 0 0 1 19 7 0 4 38 9 0 4 101 6 0 4 146 0 6 25 4 0 4 LEFT FRONT DO NOT BLOCK THE BREATHER HOLE Figure 58 Top and side views of 60 GB 120 GB models with mechanical dimensions All dimensions are...

Page 66: ...limeters The breather hole must be kept uncovered in order to keep the air pressure inside of the disk enclosure equal to external air pressure The following table shows the physical dimensions of the...

Page 67: ...View 5 6 7 Bottom View 1 2 3 4 I F Connector 4X Max penetration 4 0 mm 6X Max penetration 4 5 mm 41 6 0 2 60 0 0 2 28 5 0 5 6 35 0 2 95 25 0 2 44 45 0 2 41 28 0 5 6 32 UNC 7 6 5 4 3 2 1 Thread Figure...

Page 68: ...r equivalent mounting hardware The recommended mounting screw torque is 0 6 1 0 Nm 6 10 Kgf cm The recommended mounting screw depth is 4 mm maximum for bottom and 4 5 mm maximum for hori zontal mounti...

Page 69: ...an square level is 0 67 G for horizontal vibration and 0 56 G for vertical 6 8 1 2 Swept sine vibration The drive will meet the criteria shown below while operating in the specified conditions No erro...

Page 70: ...h a 10 G half sine shock pulse of 11 ms duration in all models No data loss occurs with a 30 G half sine shock pulse of 4 ms duration in all models No data loss occurs with a 55 G half sine shock puls...

Page 71: ...11 75 All models 400 2 disk models 2 350 1 and 3 disk models Duration ms Accleration level G Models Figure 65 Sinusoidal shock wave 6 8 5 Rotational shock All shock inputs shall be applied around the...

Page 72: ...disk models 1 and 3 disk models Max Typical Mode Figure 67 Sound power levels Mode definition Idle mode The drive is powered on disks spinning track following unit ready to receive and respond to inte...

Page 73: ...e statement Made by IBM Japan Ltd or IBM approved equivalent A label containing the drive model number the manufacturing date code the formatted capacity the place of manufacture UL CSA TUV CE C Tick...

Page 74: ...oned for safe handling in regards to sharp edges and corners 6 11 5 Environment The product does not contain any known or suspected carcinogens Environmental controls meet or exceed all applicable gov...

Page 75: ...Class 2 ESD environment specified in IBM Corporate Standard C S 2 0001 005 Radiated Electromagnetic Susceptibility RES as specified in IBM Corporate Standard C S 2 0001 012 Spectrum Management Agency...

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Page 77: ...Part 2 Interface specification Deskstar 120GXP hard disk drive specifications 63...

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Page 79: ...he system to which the device is attached Host The Deskstar 120GXP hard disk drive Device 7 2 Deviations from standard The device conforms to the referenced specifications with the following deviation...

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Page 81: ...Data bus high impedance x 0 1 A N Not used Data bus high impedance x x 0 A N Control block registers Not used Data bus high impedance x x x N N WRITE DIOW READ DIOR DA0 DA1 DA2 CS1 CS0 Functions Addr...

Page 82: ...Register 8 3 Cylinder High Register This register contains the high order bits of the starting cylinder address for any disk access At the end of the command this register is updated to reflect the c...

Page 83: ...set RST 1 and wait for at least 5 s before setting RST 0 to ensure that the device recognizes the reset IEN Interrupt Enable When IEN 0 and the device is selected device interrupts to the host will be...

Page 84: ...s the least significant bit At command completion these bits are updated to reflect the currently selected head The head number may be from zero to the number of heads minus one In LBA mode HS3 throug...

Page 85: ...A R T Function Set command and Format Unit command 8 11 Sector Count Register This register contains the number of sectors of data requested to be transferred on a read or write operation between the...

Page 86: ...Register is read by the host DSC Device Seek Complete DSC 1 indicates that a seek has completed and the device head is settled over a track DSC is set to zero by the device just before a seek begins W...

Page 87: ...CHS set by Initialize Device Parameter Multiple mode Write Cache Read look ahead ECC bytes O O O PDIAG handshake X O O DASP handshake O O O Initialization of registers 2 X X O Spinning spindle X X O I...

Page 88: ...e Error Default Value Register Figure 76 Default Register Values The meaning of the Error Register diagnostic codes resulting from power on hard reset or the Execute Device Diagnostic command are show...

Page 89: ...d Device 1 if it is present in order to indicate device active Execute Device Diagnostic If Device 1 is present Device 0 shall read PDIAG to determine when it is valid to clear the BSY bit and if Devi...

Page 90: ...nslation mode but cannot exceed 65535 0FFFFh When the host selects a CHS translation mode using the INITIALIZE DEVICE PARAMETERS command the host requests the number of sectors per logical track and t...

Page 91: ...mand and the results are indeterminate If any error occurs the command queue is aborted When the device is ready to continue processing a bus released command and BSY and DRQ are both cleared to zero...

Page 92: ...Mode command enables a host to determine if a device is currently in going into or leaving standby mode The Idle and Idle Immediate commands move a device to idle mode directly from the active or stan...

Page 93: ...Inactive No X X Sleep Inactive Yes 1 O Standby Active Yes 1 O Idle Active Yes X X Active Media Interface active RDY BSY Mode Figure 79 Power conditions Ready RDY is not a power condition A device may...

Page 94: ...r faulty condition 9 7 3 Attribute thresholds Each attribute value has a corresponding attribute threshold limit which is used for direct comparison to the attribute value to indicate the existence of...

Page 95: ...he self test features which are initiated by SMART Execute Off line Immediate command The self test checks the fault of the device reports the test status in Device Attributes Data and stores the test...

Page 96: ...urity Freeze Lock command It cannot quit this mode until power off 9 8 2 Security level The following security levels are provided High level security When the device lock function is enabled and the...

Page 97: ...word command without enabling the Device Lock Function The Master Password Revision Code is set to FFFEh as shipping default by the drive manufacturer 9 8 4 2 User Password setting When a User Passwor...

Page 98: ...ord Erase Unit Password Match Reject Complete Complete Erase Unit Lock function Disable Normal operation All commands are available Freeze Lock command Enter Device Frozen mode Normal Operation except...

Page 99: ...h Master Password Normal operation Figure 82 Password Lost 9 8 4 5 Attempt limit for SECURITY UNLOCK command The SECURITY UNLOCK command has an attempt limit The purpose of this attempt limit is to pr...

Page 100: ...s Executable Executable Command aborted Read Sector s Executable Executable Executable Read Native Max Address Executable Executable Command aborted Read Multiple Executable Executable Command aborted...

Page 101: ...Automatic Off Line Executable Executable Executable SMART Write Log Sector Executable Executable Executable SMART Read Log Sector Executable Executable Executable SMART Save Attribute Values Executabl...

Page 102: ...GB besides flagged media defects not visible by the system 2 Preparation of drives by the system manufacturer Special utility software is required to define the size of the protected area and to store...

Page 103: ...during the cur rent power on cycle The password does not persist over a power cycle but does persist over a hardware or software reset This password is not related to the password used for the Securit...

Page 104: ...al seek operation for the next seek command starts immediately after the actual seek operation for the first seek command is completed In other words the execution of two seek commands overlaps exclud...

Page 105: ...ard reset If the number of the spare sector reaches 0 sector the Reassign function will be automatically disabled The spare sectors for reassignment are located in the reserved area As a result of rea...

Page 106: ...e device needs the Set Features command to spin up into active state 9 15 Advanced Power Management feature set APM This feature allows the host to select an advanced power management level The advanc...

Page 107: ...ess Offset Feature Computer systems perform initial code loading booting by reading from a predefined address on a drive To allow an alternate bootable operating system to exist in a system reserved a...

Page 108: ...ress Any commands which access sectors across the LBA M R are aborted with error Accessible User area Accessible System reserved area LBA 0 LBA M R LBA M Figure 86 Device address map before and after...

Page 109: ...is used by the device to signal most but not all times when the BSY bit is changed from one to zero during command execution A command shall only be interrupted with a hardware or software reset The r...

Page 110: ...device clears the interrupt in response to the Status Register being read e The host reads one sector of data via the Data Register f The device sets DRQ 0 after the sector has been transferred to the...

Page 111: ...s decided by mode select bit bit 6 of Device Head register on issuing the command If an Uncorrectable Data Error UNC 1 occurs the defective data will be transferred from the media to the sector buffer...

Page 112: ...it is ready to receive a sector or block b The host writes one sector or block of data via the Data Register c The device sets BSY 1 after it has received the sector or block d When the device has fin...

Page 113: ...ccurs the device will set BSY 0 and ERR 1 store the error status in the Error Register and interrupt the host The registers will contain the location of the sector in error The errored location will b...

Page 114: ...e Operations SMART Execute Off line Data Collection SMART Return Status SMART Save Attribute Values SMART Enable Disable Automatic Off Line Standby Standby Immediate Execution of these commands involv...

Page 115: ...the DMA channel prior to reading status from the device The DMA protocol allows high performance multitasking operating systems to eliminate processor over head associated with PIO transfers 1 Host i...

Page 116: ...is ready for data transfer REL is cleared a the host transfers the data for the command identified by the Tag number using the DMA transfer protocol currently in effect b the device generates an inte...

Page 117: ...5 1 1 0 0 1 0 0 1 C9 Read DMA 4 1 1 0 0 1 0 0 0 C8 Read DMA 4 1 1 1 0 0 1 0 0 E4 Read Buffer 1 0 0 0 0 0 0 0 0 00 NOP 3 1 0 0 1 0 0 0 1 91 Initialize Device Parameters 3 1 0 0 1 0 1 0 1 95 Idle Immed...

Page 118: ...0 0 0 0 B0 SMART Save Attribute Values 3 1 0 1 1 0 0 0 0 B0 SMART Return Status 3 1 0 1 1 0 0 0 0 B0 SMART Read Attribute Thresholds 1 1 0 1 1 0 0 0 0 B0 SMART Read Attribute Values 1 1 0 1 1 0 0 0 0...

Page 119: ...able Operations D8 B0 SMART Enable Operations D6 B0 SMART Write Log D5 B0 SMART Read Log D4 B0 SMART Execute Off line Data Collection D3 B0 SMART Save Attribute Values D2 B0 SMART Enable Disable Attri...

Page 120: ...ex character is not used Indicates that the bit is not used Input Registers 0 Indicates that the bit is always set to zero 1 Indicates that the bit is always set to one H Head number Indicates that th...

Page 121: ...0 0 0 0 ERR IDX COR DRQ DSC DF RDY BSY AMN T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 90 Check Power Mode Command E5h 98h The Check Power Mode comma...

Page 122: ...al Device Configuration Overlay feature set commands are identified by the value placed in the Features register The table below shows these Features register values Reserved other DEVICE CONFIGURATIO...

Page 123: ...y that modifies some of the bits set in words 63 82 83 84 and 88 of the IDENTIFY DEVICE command response When the bits in these words are cleared the device no longer supports the indicated command mo...

Page 124: ...ported 1 Data Structure revision 0001h 0 Content Word Figure 93 Device Configuration Overlay Data structure Note Bits 7 0 of this word contain the value A5h Bits 15 8 of this word contain the data str...

Page 125: ...V 0 V V V V V V V V ERR IDX COR DRQ DSC DF RDY BSY AMN T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 95 Execute Device Diagnostic Command 90h The Execut...

Page 126: ...2 1 0 Register Command Block Input Registers Command Block Output Registers V 0 V 0 V 0 0 0 V 0 0 0 0 0 ERR IDX COR DRQ DSC DF RDY BSY AMN T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Stat...

Page 127: ...not verified with read operation whether the sector of data is initialized correctly Any data previously stored on the track will be lost The host may transfer a sector of data containing a format ta...

Page 128: ...ster specifies current LBA address bits 8 15 Low 16 23 High H In LBA mode this register specifies current LBA address bits 24 27 L 1 Error The Error Register An Abort error ABT 1 will be returned when...

Page 129: ...fter command completion of this command and are used at next power on reset or hard reset Previous information of reassign and defect are erased from the device by executing this command Note that the...

Page 130: ...ctor Count see below Error Feature Data Data 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Register Command Block Input Registers Command Block Output Registers V 0 0 V 0 0 0 V 0 0 0 0 0 ERR IDX COR DRQ DS...

Page 131: ...unique length is selected via set feature cmd 0028H 22 Buffer size in 512 byte increments XXXXH 21 Controller type 0003 dual ported multiple sector buffer with look ahead read 0003H 20 Serial number i...

Page 132: ...mber of User Addressable Sectors Word 60 specifies the low word of the number XXXXH 60 61 Current Multiple setting Bit assignments 15 9 0 Reserved 8 1 Multiple Sector Setting is Valid 7 0 xxh Current...

Page 133: ...DOWNLOAD MICROCODE command 5BEAH 83 Command set supported 15 0 Reserved 14 1 NOP command 13 1 READ BUFFER command 12 1 WRITE BUFFER command 11 0 Reserved 10 1 Host Protected Area feature set 9 0 DEVI...

Page 134: ...omatic Acoustic Management enabled 8 Set Max Security extensions enabled 7 Set Features Address Offset mode 6 Set Features subcommand required to spin up after power up 5 Power Up In Standby feature s...

Page 135: ...1 assert 0 not assert 10 9 How to determine the device number 00 Reserved 01 Jumper 10 CSEL signal 11 Some other method 8 Shall be set to one if Dev 1 7 0 Dev 0 H W reset result 7 Reserved 6 Respond f...

Page 136: ...ed 0000H 160 254 Reserved XXXXH 130 159 Current Set Feature Option Bit assignments 15 4 Reserve 3 Auto reassign 1 Enable 2 Reverting 1 Enable 1 Read Look ahead 1 Enable 0 Write Cache 1 Enable XXXXH 12...

Page 137: ...mode is entered the device is spun up to operating speed If the device is already spinning the spin up sequence is not executed During Idle mode the device is spinning and ready to respond to host com...

Page 138: ...0 0 0 0 ERR IDX COR DRQ DSC DF RDY BSY AMN T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 107 Idle Immediate Command E1h 95h The Idle Immediate command...

Page 139: ...number of heads minus 1 per cylinder Words 54 58 in Identify Device Information reflect these parameters The parameters remain in effect until the following events occur Another Initialize Device Para...

Page 140: ...nput Registers Command Block Output Registers V 0 0 V 0 0 0 V 0 0 0 0 0 ERR IDX COR DRQ DSC DF RDY BSY AMN T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure...

Page 141: ...DSC DF RDY BSY AMN T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 110 Read Buffer Command E4h The Read Buffer command transfers a sector of data from the...

Page 142: ...Data Register 16 bits at a time The host initializes a slave DMA channel prior to issuing the command The data transfers are qualified by DMARQ and are performed by the slave DMA channel The device i...

Page 143: ...er of the last transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register con...

Page 144: ...ed Command C7h This command executes in a similar manner to a READ DMA command The device may perform a bus release or it may execute the data transfer without performing a bus release if the data is...

Page 145: ...rforms a bus release This bit is set to one when the device is ready to transfer data Input parameters from the device on command complete Sector Count Bits 7 3 Tag contain the Tag of the completed co...

Page 146: ...e been transferred the device will keep setting DRQ 1 to indicate that the device is ready to transfer the ECC bytes to the host The data is transferred 16 bits at a time the ECC bytes are transferred...

Page 147: ...er contains current LBA bits 8 15 Low 16 23 High L 1 H The head number of the transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 It should be noted that the device in...

Page 148: ...to the host The sectors are transferred through the Data Register 16 bits at a time Command execution is identical to the Read Sectors command except that an interrupt is generated for each block as...

Page 149: ...7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H The head number of the last transferred sec...

Page 150: ...6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 115 Read Native Max LBA CYL F8h This command returns the native max LBA CYL of the drive which is not effected by Set Max Address command Inpu...

Page 151: ...ctors command reads one or more sectors of data from disk media and then transfers the data from the device to the host The sectors are transferred through the Data Register 16 bits at a time If an un...

Page 152: ...ansferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA...

Page 153: ...ectors verifies one or more sectors on the device No data is transferred to the host The difference of Read Sectors command and Read Verify Sectors command is whether the data is transferred to the ho...

Page 154: ...sferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA b...

Page 155: ...mmand Block Input Registers Command Block Output Registers V 0 V 0 V 0 0 V V 0 0 0 0 0 ERR IDX COR DRQ DSC DF RDY BSY AMN T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error...

Page 156: ...ing information specified in the figure below Then the device checks the transferred password If the User Password or Master Password matches the given password the device disables the security mode f...

Page 157: ...0 0 0 0 ERR IDX COR DRQ DSC DF RDY BSY AMN T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 121 Security Erase Prepare Command F3h The Security Erase Prep...

Page 158: ...data sectors and then disables the device lock function Note that the Security Erase Unit command initializes from LBA 0 to Native MAX LBA The Host MAX LBA set by the Initialize Drive Parameter or th...

Page 159: ...he security erase prepare command should be completed immediately prior to the Security Erase Unit command If the device receives a Security Erase Unit command without a prior Security Erase Prepare c...

Page 160: ...N T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 124 Security Freeze Lock Command F5h The Security Freeze Lock Command allows the device to enter frozen...

Page 161: ...sword Command F1h The Security Set Password command enables security mode feature device lock function and sets the master password or the user password The security mode feature device lock function...

Page 162: ...vice accepts the command with a value of 0000h or FFFFh in this field but does not change the Master Password Revision code The setting of the Identifier and Security level bits interacts as follows I...

Page 163: ...and is completed the device will be in device lock mode The password has not been changed yet The Security Unlock command requests to transfer a single sector of data from the host including infor mat...

Page 164: ...regards Password as Master Password The user can detect if the attempt to unlock the device has failed due to a mismatched password as this is the only reason that an abort error will be returned by t...

Page 165: ...The Seek command initiates a seek to the designated track and selects the designated head The device need not be formatted for a seek to execute properly Output parameters to the device Sector Number...

Page 166: ...vice Command A2h The Service command is used to provide data transfer and or status of a command that was previously bus released Output parameters to the device D Selected device Input parameters fro...

Page 167: ...following parameters which affect the execution of certain features as shown in below table ABT will be set to 1 in the Error Register if the Feature register contains any undefined values Output par...

Page 168: ...1 nnn nnn 000 001 010 011 100 Multiword DMA mode x 00100 nnn nnn 000 001 010 Ultra DMA mode x 01000 nnn nnn 000 001 010 011 100 101 11 29 2 Write Cache If the number of auto reassigned sectors reaches...

Page 169: ...ure register is 42h Enable Automatic Acoustic Management the Sector Count Register specifies the Automatic Acoustic Management level FF Aborted C0 FEh Set to Normal Seek mode 80 BFh Set to Quiet Seek...

Page 170: ...Native Max Address command and regards it as a Set Max security extensions command according to feature register value Valid features values are as shown below 1 01h indicates Set Max Set Password com...

Page 171: ...igh which is to be set L 1 In CHS mode this register contains cylinder number which is to be set L 0 H In LBA mode this register contains LBA bits 24 27 which is to be set L 1 In CHS mode this registe...

Page 172: ...C 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 133 Set Max Set Password If this command is immediately preceded by a Read Native Max Address command the device regards it as a...

Page 173: ...X COR DRQ DSC DF RDY BSY AMN T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 135 Set Max Lock If this command is immediately preceded by a Read Native Max...

Page 174: ...s command is immediately preceded by a Read Native Max Address command the device regards it as Set Max Address command This command requests a transfer of a single sector of data from the host includ...

Page 175: ...DSC DF RDY BSY AMN T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 137 Set Max Freeze Lock F9h If the Set Max Freeze Lock command is immediately preceded...

Page 176: ...gister Figure 138 Set Multiple Command C6h The Set Multiple command enables the device to perform Read and Write Multiple commands and estab lishes the block size for these commands The block size is...

Page 177: ...ock Output Registers V 0 V 0 V 0 0 0 V 0 0 0 0 0 ERR IDX COR DRQ DSC DF RDY BSY AMN T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 139 Sleep Command E6h...

Page 178: ...V 0 V 0 V 0 ERR IDX COR DRQ DSC DF RDY BSY AMN T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 140 S M A R T Function Set Command B0h The S M A R T Funct...

Page 179: ...esholds information to the host 11 33 1 3 SMART Enable Disable Attribute Autosave Subcommand D2h This subcommand enables and disables the Attribute Autosave feature of the device The SMART Enable Disa...

Page 180: ...es command completion before executing the specified routine During execution of the routine the device will not set BSY nor clear DRDY If the device is in the process of performing its routine and is...

Page 181: ...SMART Disable Operations subcommand from the host all other S M A R T subcommands with the exception of SMART Enable Operations are disabled and invalid and will be aborted by the device including the...

Page 182: ...Attribute Values subcommand All multibyte fields shown in these data structures are in byte ordering that is the least significant byte occupies the lowest numbered byte address location in the field...

Page 183: ...Number indicates an active attribute The device supports the following Attribute ID Numbers Ultra DMA CRC Error Count 199 Off line Scan Uncorrectable Sector Count 198 Current Pending Sector Count 197...

Page 184: ...Automatic Off line Data Collection is enabled 0 Automatic Off line Data Collection is disabled Bits 0 thru 6 represents a hexadecimal status value reported by the device Value Definition 0 Off line d...

Page 185: ...subcommand is implemented 0 SMART Execute Off line Immediate subcommand is not implemented Execute Off line Immediate implemented bit 0 Definition Bit 11 33 2 7 S M A R T capability This word of bit...

Page 186: ...0th Device Attribute 02h 12 1st Device Attribute 0010h 00h 2 Data Structure Revision Number Value Offset Byte Description Figure 144 Device Attribute Thresholds Data Structure 11 33 3 1 Data Structure...

Page 187: ...ucture checksum 1C6h 57 Reserved 1C4h 2 Device error count 16Ah 90 5th error log data structure 110h 90 4th error log data structure B6h 90 3rd error log data structure 5Ch 90 2nd error log data struc...

Page 188: ...te Description Figure 147 Error log data structure Command data structure Data format of each command data structure is shown below 12 08h 4 Time stamp ms from Power On 07h 1 Command register 06h 1 De...

Page 189: ...1 Sector number register 02h 1 Sector count register 01h 1 Error register 00h 1 Reserved Offset Byte Description Figure 149 Error data structure The state field contains a value indicating the device...

Page 190: ...lf test execution status n 18h 02h 1 Self test number 00h 2 Data structure revision Offset Byte Description Figure 150 Self test log data structure The data structure contains the descriptor of Self t...

Page 191: ...mand subcommand other than SMART ENABLE OPERATIONS was received by the de vice while the device was in a S M A R T Disabled state 04h 51h A S M A R T FUNCTION SET command was received by the device wi...

Page 192: ...6 7 Status Register Error Register Figure 152 Standby Command E2h 96h The Standby command causes the device to enter the Standby Mode immediately and to set the auto power down time out parameter sta...

Page 193: ...10 seconds 254 8 hours 253 21 minutes 252 Value 240 x 30 minutes 241 251 Value x 5 seconds 1 240 Timer disabled 0 Time out Value When the automatic power down sequence is enabled the drive will enter...

Page 194: ...T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 153 Standby Immediate Command E0h 94h The Standby Immediate command causes the device to enter Standby mo...

Page 195: ...V 0 0 0 0 0 ERR IDX COR DRQ DSC DF RDY BSY AMN T0N ABT 0 IDN 0 UNC CRC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Status Register Error Register Figure 154 Write Buffer Command E8h The Write Buffer command trans...

Page 196: ...ansferred through the Data Register 16 bits at a time The host initializes a slave DMA channel prior to issuing the command Data transfers are qualified by DMARQ and are performed by the slave DMA cha...

Page 197: ...ansferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA...

Page 198: ...d Command CCh This command executes in a similar manner to a WRITE DMA command The device may perform a bus release or it may execute the data transfer without performing a bus release if the data is...

Page 199: ...e performs a bus release This bit is set to 1 when the device is ready to transfer data Input parameters from the device on Command Complete Sector Count Bits 7 3 Tag contain the Tag of the completed...

Page 200: ...tes are then written to the disk media After 512 bytes of data have been transferred the device will keep setting DRQ 1 to indicate that the device is ready to receive the ECC bytes from the host The...

Page 201: ...5 Low 16 23 High L 1 H The head number of the sector to be transferred L 0 In LBA mode this register contains current LBA bits 24 27 L 1 The drive internally uses 52 bytes of ECC on all data read or w...

Page 202: ...disk media Command execution is identical to the Write Sectors command except that an interrupt is generated for each block as defined by the Set Multiple command instead of for each sector The sector...

Page 203: ...0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H The head number of the last transferred s...

Page 204: ...Sectors command transfers one or more sectors from the host to the device the data is then written to the disk media The sectors are transferred through the Data Register 16 bits at a time If an unco...

Page 205: ...ansferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA...

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Page 207: ...BSY 1 OUT To Command Register Device Busy After Command Code Out Data In Command 31 sec Status Register BSY 0 and RDY 1 Bus RESET Signal Asserted Device Ready After Hard Reset 400 ns Status Register B...

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Page 209: ...9 Drive ready time 15 DRQ interval time 28 E ECC On The Fly correction 50 Electrical interface 21 Electromagnetic compatibility 62 F Flammability 61 Formatted Capacity 9 Full stroke seek 14 G General...

Page 210: ...Reset timings 26 S S M A R T 79 Safety 61 Sector Addressing Mode 76 Security 81 Seek Overlap 89 Shipped format 19 Shipping conditions 45 Shock 56 Signal definition 22 Signal timings 26 Simple sequent...

Page 211: ...istered trademark of International Business Machines Corporation Other company product and service names may be trademarks or service marks of others Product description data represents IBM s design o...

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