IBM 88743BU - System x3950 E, User Manual

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Chapter 1. Technical overview
35
The Xeon E7210 and E7300 Tigerton processors have two levels of cache on the
processor die:
򐂰
Each pair of cores in the processor has either 2, 3, or 4 MB shared L2 cache
for a total of 4, 6, or 8 MB of L2 cache. The L2 cache implements the
Advanced Transfer Cache technology.
򐂰 L1 execution trace cache in each core is used to store micro-operations and
decoded executable machine instructions. It serves those to the processor at
rated speed. This additional level of cache saves decode-time on cache-hits.
The Tigerton processors do not have L3 cache.
Figure 1-15 compares the layout of the Tigerton dual-core and quad-core
processors.
Figure 1-15 Comparing the dual-core and quad-core Tigerton
The Xeon E7400 Series Dunnington processors, both 4-core and 6-core models,
have shared L2 cache between each pair of cores but also have a shared L3
cache across all cores of the processor. While technically all Dunnington Xeon
processors have 16MB of L3 cache, 4-core models only have 12MB of L3 cache
enabled and available. See Figure 1-16 on page 36.
L1 Instruct
Cache
L1 Data
Cache
L2
Cache
Quad-core Xeon E7300 series
(Code name: Tigerton)
L2
Cache
L1
Instruct
Cache
L1
Data
Cache
Processor
Core
L2
Cache
Dual-core Xeon E7210
(Code name: Tigerton)
L1
Instruct
Cache
L1
Data
Cache
Processor
Core
L2
Cache
Processor
Core
L1 Instruct
Cache
L1 Data
Cache
L1 Instruct
Cache
L1 Data
Cache
L1 Instruct
Cache
L1 Data
Cache
Processor
Core
Processor
Core
Processor
Core