37
Dio5SetOutput(0x00);
//clear
//
DIO = Dio5GetInput() & 0x0F;
Dio5SetOutput(0x00);
//clear
DIO = Dio5GetInput() & 0x0F;
if (DIO != 0x0A)
{
printf("The Fintek 81865 digital IO abnormal, abort.\n");
return(1);
}//if (DIO != 0x0A)
Dio5SetOutput(0xA0);
//clr#
is
high
Dio5SetOutput(0xF0);
//clk
and
clr#
is
high
Dio5SetOutput(0xA0);
//clr#
is
high
DIO = Dio5GetInput() & 0x0F;
if (DIO != 0x05)
{
printf("The Fintek 81865 digital IO abnormal, abort.\n");
return(1);
}
printf("!!! Pass !!!\n");
return
0;
}
//---------------------------------------------------------------------------
void Dio5Initial(void)
{
unsigned char ucBuf;
//switch GPIO multi-function pin for
gpio 50~57
//gpio53~57 UR5_FULL_EN(bit1), clear UR6_FULL_EN(bit3)
//set UR5_FULL_EN,should set UR_GP_PROG_EN = 1 (reg26,bit0) first
ucBuf = Get_F81865_Reg(0x26);
ucBuf |= BIT0;
Set_F81865_Reg(0x26,
ucBuf);
//set UR5_FULL_EN(bit1), clear UR6_FULL_EN(bit3)
ucBuf = Get_F81865_Reg(0x2A);
ucBuf &= ~BIT3;//clear bit 3,
ucBuf |= BIT1;//set bit 1,
Set_F81865_Reg(0x2a,
ucBuf);
//GPIO51 ~ GPIO52
//clear
UR6_ALT_EN(bit5),
IR_ALT_EN(bit4),set FDC_GP_EN(bit3)
//GPIO50
//set FDC_GP_EN(bit3), clear RTS6_ALT_EN(RTS6_2_ALT_EN)(bit6)
ucBuf = Get_F81865_Reg(0x2A);
ucBuf &= ~(BIT4+BIT5+BIT6); //clear UR6_ALT_EN(bit5), IR_ALT_EN(bit4),
RTS6_ALT_EN(RTS6_2_ALT_EN)(bit6)
Set_F81865_Reg(0x2a,
ucBuf);
//set FDC_GP_EN(bit3), should clear UR_GP_PROG_EN (reg26,bit0) first
ucBuf = Get_F81865_Reg(0x26);
ucBuf &= ~BIT0;
Set_F81865_Reg(0x26,
ucBuf);//clear UR_GP_PROG_EN = 0 (reg26,bit0)
ucBuf = Get_F81865_Reg(0x2A);
ucBuf |= BIT3; //set FDC_GP_EN(bit3),
Set_F81865_Reg(0x2a,
ucBuf);
Set_F81865_LD(0x06);
//switch
to
logic
device
6
//enable the GP5 group
