Hyundai PD421, Svc Manual

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Plasma Display PD421
Transmitter Switching Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
TPPos0 TransmitterOutputPulse Positionfor Bit 0 (Figures 13, 14)
(Note 5)
f = 85 MHz -0.20 0 0.20 ns
TPPos1 TransmitterOutput Pulse Position for Bit 1
TransmitterOutput Pulse Position for Bit 2
TransmitterOutput Pulse Position for Bit 3
TransmitterOutput Pulse Position for Bit 4
TransmitterOutput Pulse Position for Bit 5
TransmitterOutput Pulse Position for Bit 6
1.48 1.68 1.88 ns
TPPos2 3.16 3.36 3.56 ns
TPPos3 4.84 5.04 5.24 ns
TPPos4 6.52 6.72 6.92 ns
TPPos5 8.20 8.40 8.60 ns
TPPos6 9.88 10.08 10.28 ns
TSTC TxIN Setup to TxCLK IN
(Figure 7)
2.5 ns
THTC TxIN Hold to TxCLK IN
(Figure 7)
TCCD TxCLK IN to TxCLK OUT Delay
(Figure 8)
T
A
= 25 C, V
CC
= 3.3V
3.8
0
6.3 ns
ns
TxCLK IN to TxCLK OUT Delay (Figure 8) 2.8 7.1 ns
TJCC TransmitterJitter Cycle-to-Cycle (Figures 15, 16) (Note 6) f = 85 MHz 110 150 ps
f = 65 MHz 210 230 ps
f = 40 MHz 350 370 ps
TPLLS Transmitter Phase Lock Loop Set (Figure 9) 10 ms
TPDD Transmitter Power DownDelay (Figure 12) 100 ns
Note 5: The Minimumand MaximumLimits are based on statisticalanalysis of the device performanceover process, voltage,and temperatureranges. This
parameteris functionality testedonlyon AutomaticTest Equipment(ATE).
Note 6: The limitsare based on benchcharacterization of the device'sjitterresponseover the powersupplyvoltagerange.Outputclockjitteris measured with a
cycle-to-cycleji/˛3nsappliedto the inputclocksignalwhiledata inputsare switching(See Figures 15 and 16).A jittereventof 3ns, represents worsecase
jumpin theclockedge frommostgraphicscontroller VGA chipscurrently available.Thisparameteris used whencalculatingsystemmarginas described in AN-1059.
AC Timing Diagrams
DS100868-4
FIGURE 1. ™Worst Case ∫ Test Pattern (Note 7)