HYUNDAI MicroElectonics
68
NO.
MNEMONIC
OP
CODE
BYTE
NO
CYCLE
NO
OPERATION
FLAG
NVGBHIZC
79
EOR #imm
A4
2
2
Exclusive OR
80
EOR dp
A5
2
3
A
( A )
⊕
( M )
81
EOR dp + X
A6
2
4
82
EOR !abs
A7
3
4
N-----Z-
83
EOR !abs + Y
B5
3
5
84
EOR [ dp + X ]
96
2
6
85
EOR [ dp ] + Y
97
2
6
86
EOR { X }
94
1
3
87
EOR1 M.bit
AB
3
5
Bit exclusive-OR C-flag : C
( C )
⊕
( M .bit )
-------C
88
EOR1B M.bit
AB
3
5
Bit exclusive-OR C-flag and NOT : C
( C )
⊕
~( M .bit )
-------C
89
INC A
88
1
2
Increment
N-----ZC
90
INC dp
89
2
4
M
( M )
1
91
INC dp + X
99
2
5
92
INC !abs
98
3
5
N-----Z-
93
INC X
8F
1
2
94
INC Y
9E
1
2
95
INCW dp
9D
2
6
Increment memory pair : ( dp+1) ( dp)
( dp+1) ( dp )
1
N-----Z-
96
JMP !abs
1B
3
3
Unconditional jump
97
JMP [!abs]
1F
3
5
PC
jump address
--------
98
JMP [dp]
3F
2
4
99
LDA #imm
C4
2
2
Load accumulator
100
LDA dp
C5
2
3
A
( M )
101
LDA dp + X
C6
2
4
102
LDA !abs
C7
3
4
103
LDA !abs + Y
D5
3
5
N-----Z-
104
LDA [ dp + X ]
D6
2
6
105
LDA [ dp ] + Y
D7
2
6
106
LDA { X }
D4
1
3
107
LDA { X }+
DB
1
4
X- register auto-increment : A
( M ) , X
X
1
108
LDC M.bit
CB
3
4
Load C-flag : C
( M .bit )
-------C
109
LDCB M.bit
CB
3
4
Load C-flag with NOT : C
~( M .bit )
-------C
110
LDM dp,#imm
E4
3
5
Load memory with immediate data : ( M )
imm
--------
111
LDX #imm
1E
2
2
Load X-register
112
LDX dp
CC
2
3
X
( M )
N-----Z-
113
LDX dp + Y
CD
2
4
114
LDX !abs
DC
3
4
115
LDY #imm
3E
2
2
Load Y-register
116
LDY dp
C9
2
3
Y
( M )
N-----Z-
117
LDY dp + X
D9
2
4
118
LDY !abs
D8
3
4
119
LDYA dp
7D
2
5
Load YA : YA
( dp +1 ) ( dp )
N-----Z-
120
LSR A
48
1
2
Logical shift right
121
LSR dp
49
2
4
7 6 5 4 3 2 1 0 C
N-----ZC
122
LSR dp + X
59
2
5
123
LSR !abs
58
3
5
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