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HYUNDAI MicroElectonics

66

3.2.  Alphabetic Order Table of Instruction

   

NO.

MNEMONIC

OP

CODE

BYTE

NO

CYCLE

NO

OPERATION

FLAG

NVGBHIZC

1

ADC   

#imm

04

2

2

Add  with  carry.

2

ADC  dp

05

2

3

    A 

 ( A ) 

 ( M ) 

  C

3

ADC  dp + X

06

2

4

4

ADC  !abs

07

3

4

NV--H--ZC

5

ADC  !abs + Y

15

3

5

6

ADC    [ dp + X ]

16

2

6

7

ADC    [ dp ] + Y

17

2

6

8

ADC  { X }

14

1

3

9

ADDW  dp

1D

2

5

16-Bits add without carry :    YA

  ( YA ) 

( dp +1 ) ( dp )

NV--H-ZC

10

AND  #imm

84

2

2

Logical AND

11

AND  dp

85

2

3

    A 

 ( A ) 

( M )

12

AND  dp + X

86

2

4

13

AND  !abs

87

3

4

N-----Z-

14

AND  !abs + Y

95

3

5

15

AND    [ dp + X ]

96

2

6

16

AND    [ dp ] + Y

97

2

6

17

AND  { X }

94

1

3

18

AND1  M.bit

8B

3

4

Bit AND C-flag      : C

 ( C ) 

  ( M .bit )

-------C

19

AND1B  M.bit

8B

3

4

Bit AND C-flag and NOT    : C

 ( C ) 

  ~( M .bit )

-------C

20

ASL    A

08

1

2

Arithmetic shift left

21

ASL    dp

09

2

4

    C        7   6   5   4   3   2   1   0

N-----ZC

22

ASL  dp + X

19

2

5

23

ASL  !abs

18

3

5

24

BBC    A.bit,rel

y2

2

4/6

Branch if bit clear :

--------

25

BBC  dp.bit,rel

y3

3

5/7

if ( bit ) 

0 , then    PC

  ( PC ) 

rel

26

BBS    A.bit,rel

x2

2

4/6

Branch if bit set :

--------

27

BBS  dp.bit,rel

x3

3

5/7

if ( bit ) 

1 , then    PC

  ( PC ) 

rel

28

BCC    rel

50

2

2/4

Branch if carry bit clear :
if ( C )

0 , then    PC

( PC )

rel

--------

29

BCS  rel

D0

2

2/4

Branch if carry bit set : if ( C )

1 , then    PC

( PC )

rel

--------

30

BEQ  rel

D0

2

2/4

Branch if equal :    if ( Z ) 

1 , then    PC

  ( PC ) 

rel

--------

31

BIT    dp

0C

2

4

Bit test A with memory :

MM----Z-

32

BIT  !abs

1C

3

5

 Z 

 ( A ) 

  ( M ) ,    N 

( M

7 

) ,    V

( M

6 

)

33

BMI  rel

90

2

2/4

Branch if minus :    if ( N ) 

1 , then    PC

  ( PC ) 

rel

--------

34

BNE  rel

70

2

2/4

Branch if not equal :    if ( Z ) 

0 , then

--------

35

BPL  rel

10

2

2/4

Branch if minus :    if ( N ) 

0 , then    PC

  ( PC ) 

rel

--------

36

BRA  rel

2F

2

4

Branch always :    PC

  ( PC ) 

rel

--------

37

BRK

0F

1

8

Software interrupt :
B 

”

1

”

,    M( SP)

( PC

H 

),  SP 

SP - 1,

M( s )

 ( PC

L 

), SP

SP - 1, M( SP)

( PSW ),

SP 

SP -1,    PC

L

( 0FFDE

H

 ) ,    PC

H

( 0FFDF

H

) .

---1-0--

38

BVC    rel

30

2

2/4

Branch if overflow bit clear :
if (V)

0 , then    PC

( PC)

rel

--------

39

BVS    rel

B0

2

2/4

Branch if overflow bit set :
if (V)

1 , then    PC

( PC )

rel

--------

”

0

 

Summary of Contents for GMS800

Page 1: ...NOV 1996 Rev 1 0 8 BIT SINGLE CHIP MICROCOMPUTERS GMS800 Series Instruction Manual ...

Page 2: ... Korea or Distributors and Representatives listed at address directory HYUNDAI MicroElectonics reserves the right to make changes to any Information here in at any time without notice The information diagrams and other data in this manual are correct and reliable however HYUNDAI MicroElectonics Co Ltd is in no way responsible for any violations of patents or other rights of the third party generat...

Page 3: ...4 1 4 Absolute Addressing Mode abs 5 1 5 Indexed Addressing Mode 6 1 6 Indirect Addressing Mode 8 1 7 Relative Addressing Mode 11 1 8 Bit Manipulation Mode 13 1 9 16 Bit Operation Mode dp 14 1 10 Etc 15 2 INSTRUCTION SET 17 3 APPENDIX 65 3 1 Instruction Map 65 3 2 Alphabetic Order Table of Instruction 66 3 3 Instruction Table by Function 71 ...

Page 4: ......

Page 5: ...sary that G8MC core user understand the various addressing modes This gives the experienced programmer flexibility for writing programs that are more sufficient in the number of instructions and the execution time This core has 10 addressing modes as shown bellows Inherent Addressing Mode Immediate Addressing Mode Direct Page Addressing Mode Absolute Addressing Mode Indexed Addressing Mode Indirec...

Page 6: ... to instructions which operate on registers A X Y PSW SP This mode has an important advantage that executes faster than any two or three byte instruction OP CODE Register Instructions A ASL DAA DAS DEC INC LSR PUSH POP ROL ROR XCN X INC PUSH POP Y INC PUSH POP A X TAX TXA XAX A Y TAY TYA XAY MUL X Y XYX X SP TSPX TXSP A X Y DIV PSW CLRC CLRG CLRV DI EI PUSH POP SETC SETG ETC BRK NOP RET RETI STOP ...

Page 7: ... Initializing registers to a constant value Immediate data must be 8 bit data Register A X Y OP CODE imm Operand Instructions A ADC AND CMP OR SBC EOR LDA X CMPX LDX Y CMPY LDY Example 04 35 ADC 35H Memory dp OP CODE imm dp Operand Instructions Memory LDM Example G 1 E4 55 35 LDM 35H 55H Op code 04 Operand 35 MEMORY A A 35h C Operand 55 Opcode E4 data Operand 35 MEMORY data 55h 0 Page 000h 0FFh 10...

Page 8: ...ge dp is determined by G flag G 0 0 Page 0000H 00FFH G 1 1 Page 0100H 01FFH OP CODE dp Operand Instructions A ADC AND CMP LDA EOR OR SBC X LDX CMPX Y LDY CMPY Memory ASL COM DEC INC LSR ROL ROR TST Example G 1 05 35 ADC 35H Example G 1 89 35 INC 35H Op code 05 data Operand 35 MEMORY A A data C 0 Page 000h 0FFh 100h 135h 1FFh 0 Page 1 Page Op code 89 data Operand 35 MEMORY data data 1 0 Page 000h 0...

Page 9: ...sing mode is to require 3 byte instruction OP CODE Low Address Upper Address Operand Instructions A ADC AND CMP LDA EOR OR SBC STA X CMPX LDX STX Y CMPY LDY STY PSW JMP CALL Memory ASL BIT DEC INC LSR ROL ROR TCLR1 TSET1 Example 07 35 D0 ADC 0D035H Example G 1 98 35 01 INC 0135H Op code 07 Operand 35 data Operand D0 MEMORY A A data C D035h Op code 98 data Operand 35 Operand 01 MEMORY data data 1 0...

Page 10: ...dex value stored in the register X register Indexed Addressing Mode in direct page dp dp X The effective address is determined by adding the address of operand and the contents of X register it is specified to direct page of memory OP CODE dp Operand Instructions A Memory ADC AND CMP LDA EOR OR SBC STA ASL DEC INC LSR ROL ROR XMA Y Memory LDY STY Example G 0 X F5h 06 45 ADC 45H X Y register Indexe...

Page 11: ...mined by adding the address of operand and the contents of Y register it is specified to all space of memory OP CODE Low Address Low Address Operand Instructions X Memory ADC AND CMP EOR LDA OR SBC STA Example Y 55h 15 35 D0 ADC 0D035H Y D035h Op code 15 Operand data Operand Y 55 MEMORY A A data C D08Ah D08Ah ...

Page 12: ...Instructions A Memory ADC AND CMP LDA EOR OR SBC STA XMA Example G 1 X 35h 14 ADC X X register Indirect Addressing Mode in direct page auto increment X The addressing method of this mode is the same as X Register indirect addressing mode except auto increment of x register OP CODE Operand Instructions A Memory LDA STA Example G 1 X 35h 14 LDA X Op code 14 data X 35 MEMORY A data X 36H 0 Page 000h ...

Page 13: ...ontents of memory pair dp X 1 dp X in direct page which is determined by adding the address of operand and the contents of X register OP CODE dp X Operand Instructions A Memory ADC AND CMP EOR LDA OR SBC STA Example G 0 X 10h 16 25 ADC 25H X 0FFh 0FFh PC C005h Op code 3F Operand 35 MEMORY 000h 100h data1 05 035h C005h 0 Page 1 Page data2 C0 NEXT 036h 0FFh 0FFh C005h A A data C Opcode 16 Operand 25...

Page 14: ...A OR SBC STA Example 17 25 ADC 25H Y Absolute Indirect Addressing Mode abs The effective address is contents of abs 1 abs OP CODE Lower Address Upper Address Operand Instructions PSW JMP Example G 0 Y 10h 1F 25 C0 JMP 0C025H 0FFh 0FFh C015h A A data C Op code 17 Operand 25 MEMORY 000h 100h C015h data1 05 025h 0 Page 1 Page data2 C0 Data 026h Y 10 C026h D005h Op code 1F Operand 25 Operand C0 MEMORY...

Page 15: ...relatives address can be specified with a smaller number of bits than the number of bits required to designate the entire memory address The relative address from the current address is in the range of 128 127 byte PSW Relative rel The branch operation is determined by the bit of PSW specified by instruction The branch address is obtained by adding the contents of operand to the contents of progra...

Page 16: ...dp rel Operand Instructions Memory BBC BBS Example G 0 0035h 55h 33 35 30 BBC 35H 1 30H Etc Mixing instruction BNE rel after CMP or DEC operation CBNE dp rel CMP dp BNE rel CBNE dp X rel CMP dp X BNE rel DBNE dp rel DEC dp BNE rel DBNE Y rel DEC Y BNE rel 1 0 1 0 1 0 1 0 0 0 1 1 3h 0035h Op code 2 3 PC 30h Op code 33 Operand 35 Operand 30 MEMORY IF M1 1 3 30 NEXT 1 035h Data 55 2 1 PC 30h Op code ...

Page 17: ...ctions A CLRA1 SETA1 Example A 00h 0B C0 SETA1 A 6 Direct Page Memory Bit Operation dp bit Bit position of memory in direct page is determined by the upper 3 bits of op code OP CODE operand Operand Instructions Memory CLR1 SET1 Example G 0 035h 00h C1 35 SET1 35H 6 1 1 0 0 0 0 0 0 0 1 1 0 0 0h Accumulator A6 A6 1 Operand 2 Op code 0B Operand C0 MEMORY NEXT 1 0035h M6 M6 1 1 1 0 0 1h Op code Op cod...

Page 18: ...OR1B LDC LDCB OR1 OR1B STC Memory NOT1 Example C 1 135h 00h 8B 35 51 AND1B 135H 2 1 9 16 Bit Operation Mode dp 2nd byte of instruction operand is offset address in direct page the contents of memory pair in its page is determined to data Direct page is selected by G flag G flag is changeable by SETG CLRG OP CODE dp Operand Instructions YA Memory ADDW CMPW LDYA STYA SUBW Memory DECW INCW Example G ...

Page 19: ...F 35 PCALL 35H Table CALL n The vector table of TCALL is determined by the upper 4bits of op code The domain of TCALL vector is in address FFC0H FFDFH OP CODE Example 4A TCALL 4 Op code 4F Operand 35 MEMORY FF00h NEXT FF35h FFFFh U Page Op code 4A MEMORY FF00h T vector1 25 FFFFh U Page T vector2 D1 FFD6h FFD7h NEXT D125h 1 0 0 0 Ah Op code reverse PC Fh Fh 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 6h Dh ...

Page 20: ...HYUNDAI MicroElectonics 16 ...

Page 21: ... instruction as function and charged bytes Charging Function Of GMS800 Series Instruction Set Function No Arithmetic Logic Operation 89 16 bit Operation 7 Register Memory Operation 44 Bit Manipulation 23 Branch Jump Operation 24 Control Operation etc 15 Total 202 Charging space of GMS800 series instruction set as bytes Size 1 Byte 2 Bytes 3 Bytes Total No 56 108 38 202 Percents 28 53 19 ...

Page 22: ...olute Address Indirect Address Register Indirect Address Register Indirect Address Register Auto Increment bit Bit Position A bit Bit Position of A Register dp bit Bit Position of Direct Page Memory M bit Bit Position of Memory 000H 0FFFH rel Relative Addressing Data upage U Page 0FF00H 0FFFFH Offset Address n Table CALL Number 0 15 x Indicate Upper Nibble of Op code Bit Position y Indicate Upper ...

Page 23: ...A0 SETC 11 F00E 0535 ADC 35H A 35H C 12 F010 DF DAA 13 14 F011 A0 SETC 15 F012 0410 ADC 10H A 10H C 16 F014 DF DAA 17 18 F015 0635 ADC 35H X 19 20 F017 151AF0 ADC DATA Y 21 22 23 F01A 14 DATA DB 14H 16H 47H 24 F01B 16 25 F01C 47 ADDW Add word without carry 16bit Function YA YA dp 1 dp Description Add the contents of memory pair dp 1 dp to 16 bit accumulator YA without carry The result is left in t...

Page 24: ... 3 4 AND abs Y 95 3 5 AND dp X 96 2 6 AND dp Y 97 2 6 AND X 94 1 3 Example 85 F6D1 C531 LDA OMODE 86 F6D3 84FB AND 11111011B 87 F6D5 E531 STA OMODE AND1 Bit logical AND Function C C M bit Description Logical AND of the carry flag and the specified bit of memory The results is left in the carry flag Flag Mnemonic OP Code Bytes Cycles AND1 M bit 8B 3 4 The bit4 of 3rd byte is set to 0 Example 64 KEY...

Page 25: ...61 62 F03F 8B1F30 AND1B F_STBY C 1FH 1 C 63 F042 5004 BCC KOR 64 F044 C4C4 LDA 0C4H 65 F046 2F02 BRA 4 66 F048 C410 KOR LDA 10H 67 F04A 6F RET ASL Arithmetic shift left Function C 7 6 5 4 3 2 1 0 Description Move the contents of the accumulator or of the memory left by one bit position 0 comes in on the right bit0 Bit7 enter into the carry flag Flag Mnemonic OP Code Bytes Cycles ASL A 08 1 2 ASL d...

Page 26: ...NEW EQU 1 23H 73 74 75 F04E 332303 BBC F_NEW QUIT IF F_NEW 0 QUIT 76 F051 E40B34 LDM 34H 0BH 1 SKIP 77 78 79 F054 6F QUIT RET BBS Branch if bit set Function if bit 1 then PC PC rel Description Branches if the specified bit of the accumulator or memory is 1 Flag Mnemonic OP Code Bytes Cycles BBS A bit rel x2 2 4 6 BBS dp bit rel x3 3 5 7 x means that the bit4 of op code is 0 Example 72 F_NEW EQU 1 ...

Page 27: ..._SLP 63 F042 5004 BCC UNCNTRL 64 F044 3EC4 LDY 0C4H 65 F046 2F02 BRA 4 66 F048 C410 UNCNTRL LDA 10H 67 F04A 6F RET BCS Branch if carry flag set Function if C 1 then PC PC rel Description Branch if carry flag is 1 Flag Mnemonic OP Code Bytes Cycles BCS rel D0 2 2 4 Example 68 F04B 8B1F20 AND1 F_SLP 69 F04E D004 BCS UNCON 70 F050 3EC4 LDY 0C4H 71 F052 2F02 BRA 4 72 F054 C410 UNCON LDA 10H 73 F056 6F...

Page 28: ...121 E08F C400 KISTATUS LDA 0 BIT Bit test Function Z A M N M7 V M6 Description Logical AND of the accumulator and the contents of memory The result effects zero flag Z and the bit7 of memory enter into negative flag N bit6 enter into overflow flag V The accumulator and the contents of memory are unchanged Flag M7M6 Mnemonic OP Code Bytes Cycles BIT dp 0C 2 4 BIT abs 1C 3 5 Example 97 E06F C40F LDA...

Page 29: ... EQU 5 108 E07C C570 LDA 70H 109 E07E 2404 SBC 4 110 E080 9002 BMI MINUS 111 E082 E505 STA WORK0 112 113 E084 CE MINUS XCN BNE Branch if not equal Function if Z 0 then PC PC rel Description Branches if zero flag Z is 0 Flag Mnemonic OP Code Bytes Cycles BNE rel 70 2 2 4 Example 712 D0A3 C556 LDA RTXHIGH 713 D0A5 440F CMP 0FH 714 D0A7 7006 BNE SUB_ON IF RTXHIGH 0FH THEN JUMP TO SUB_ON ...

Page 30: ...DA 30H X 188 F0E7 E640 STA 40H X 189 F0E9 AF DEC X 190 F0EA 10F9 BPL CONTI 191 F0EC FF NOP BRA Branch always Function PC PC rel Description Unconditional short branch Flag Mnemonic OP Code Bytes Cycles BRA rel 2F 2 4 Example 156 E0B5 E40330 PROGA LDM 30H 3H 157 E0B8 E40D31 LDM 31H 0DH 158 E0BB E40F32 LDM 32H 0FH 159 E0BE E40933 LDM 33H 9H 160 E0C1 E40034 LDM 34H 0H 161 E0C4 E40335 LDM 35H 3H 162 E...

Page 31: ...0F 1 8 Example 165 E0CC E0 EI 166 E0CD 0F BRK PUSH THE CONTENTS OF PC AND PSW TO STACK 167 E0CE 88 INT2 INC A 168 169 170 E0CF 3BC4E0 SOFTINT CALL ADSEL 171 E0D2 7F RETI BVC Branch if overflow flag clear Function if V 0 then PC PC rel Description Branches if overflow flag V is 0 Flag Mnemonic OP Code Bytes Cycles BVC rel 30 2 2 4 Example 175 E0D3 D51AE0 LDA DATA Y 176 E0D6 0510 ADC 10H 177 E0D8 30...

Page 32: ...tes Cycles BVS rel B0 2 2 4 Example 179 E0DA D51AE0 LDA DATA Y 180 E0DD 0555 ADC 55H 181 E0DF B0CD BVS OVERL CALL Subroutine call Function M SP PCH SP SP 1 M SP PCL SP SP 1 if abs PC abs if dp PCL dp PCH dp 1 Description Subroutine call Flag Mnemonic OP Code Bytes Cycles CALL abs 3B 3 8 CALL dp 5F 2 8 Example 184 E0E1 C403 LDA 3 A 3 185 E0E3 3BF6E0 CALL KREAD ...

Page 33: ...s of memory are not changed Flag Mnemonic OP Code Bytes Cycles CBNE dp rel FD 3 5 7 CBNE dp X rel 8D 3 6 8 Example 144 E0A6 C4A4 LDA 0A4H 145 E0A8 FD440B CBNE INFM TIN TEST INFM 0A4H CLR1 Clear bit Function dp bit 0 Description Clear the specified bit of memory Flag Mnemonic OP Code Bytes Cycles CLR1 dp bit y1 2 4 y means that the bit4 of op code is 1 Example 220 E100 5143 CLR1 43H 2 221 E102 2F02...

Page 34: ...ode Bytes Cycles CLRA1 A bit 2B 2 2 Example 225 E107 2BA0 CLRA1 A 5 226 E109 2F02 BRA LPD3 227 E10B 0BA0 SETA1 A 5 228 E10D FF LPD3 NOP CLRC Clear carry flag Function C 0 Description Clear carry flag Flag Mnemonic OP Code Bytes Cycles CLRC 20 1 2 Example 210 E0F7 A0 SETC 211 E0F8 2F01 BRA LPA6 212 E0FA 20 CLRC 213 E0FB FF LPA6 NOP ...

Page 35: ...mple 262 E12D C0 SETG 263 E12E C530 LDA 30H LOAD FROM 0130H 264 E130 40 CLRG 265 E131 E505 STA WORK0 STORE TO 0005H CLRV Clear overflow flag Function V 0 H 0 Description Clear overflow flag V and half overflow flag H Flag Mnemonic OP Code Bytes Cycles CLRV 80 1 2 Example 238 E112 20 CLRC 239 E113 0409 ADC 09H 240 E115 80 CLRV ...

Page 36: ...4 1 3 Example 243 E116 C533 LDA 33H 244 E118 4414 CMP 14H 245 E11A F0F6 BEQ OPROG 241 QMODE EQU 0BFH 247 E11C C533 LDA 33H 248 E11E 45BF CMP QMODE 249 E120 F0F0 BEQ OPROG CMPX Compare X register Function X M Description Compare the X register with the contents of memory or immediate data The results effects N Z C and the X register and the contents of memory are unchanged Flag Mnemonic OP Code Byt...

Page 37: ... 253 E124 9E CNTLOOP INC Y 254 E125 D51AE0 LDA DATA Y 255 E128 9F TAY 256 E129 7E05 CMPY 5H 257 E12B F0F7 BEQ CNTLOOP CMPW Compare word YA Function YA dp 1 dp Description Compare the 16bit accumulator YA with memory pair 16bit The results effects N Z C and the YA and the contents of memory are unchanged Flag Mnemonic OP Code Bytes Cycles CMPW dp 5D 2 4 Example 531 C245 BD05 DECW CMPDATL 532 C247 5...

Page 38: ...H A7 A4 hex A3 A0 hex ADDED C 0 0 0 9 0 9 00 0 0 0 0 8 A F 06 0 0 1 0 9 0 3 06 0 0 0 A F 0 9 60 1 0 0 9 F A F 66 1 0 1 A F 0 3 66 1 1 0 0 2 0 9 60 1 1 0 0 2 A F 66 1 1 1 0 3 0 3 66 1 Description After addition convert the hex data of accumulator to decimal data Flag Mnemonic OP Code Bytes Cycles DAA DF 1 3 Example DECIMAL COUNT FROM 0 TO 999999 427 F882 1E02 LDX 2 428 F884 A0 SETC 429 F885 C400 CO...

Page 39: ...AL SUBTRACTION 418 419 F870 A0 SETC set carry 420 F871 C456 LDA 56H 56H A 421 F873 2487 SBC 87H Acc 56H 87H 422 F875 CF DAS Acc 69H 423 F876 E533 STA DA_CNT DBNE Decrement and branch if not equal Function M M 1 if Z 0 then PC PC rel Description Decrement the contents of memory by 1 If the result is not zero branch to specified address Flag Mnemonic OP Code Bytes Cycles DBNE dp rel AC 3 5 7 DBNE Y ...

Page 40: ...F86A 3934 NextByte ROL 34H X SHIFT ROTATE LEFT 410 F86C AF DEC X DECREMENT INDEX COUNTER 411 F86D 10FB BPL NextByte 412 F86F 6F RET DECW Decrement word 16bit Function dp 1 dp dp 1 dp 1 Description Decrement the contents of 16bit memory pair by 1 Flag Mnemonic OP Code Bytes Cycles DECW dp BD 2 6 Example 529 C241 C40F LDA 0FH 530 C243 3E3F LDY 03FH 531 C245 BD05 DECW CMPDATL 532 C247 5D05 CMPW CMPDA...

Page 41: ...7 C006 5EC0 CMPX 0C0H 248 C008 70F9 BNE RAM_CLR DIV Divide Function YA X Q A R Y Description Divide 16bit accumulator YA by the X register The quotient is left in the accumulator and The remainder is left in the Y register Flag Mnemonic OP Code Bytes Cycles DIV 9B 1 12 Example 464 C1D9 1E0A HDCON LDX 10 LOAD DIVISOR 465 C1DB 3E00 LDY 0 LOAD DIVIDEND HIGH 466 C1DD C50C LDA ECD LOAD DIVIDEND LOW SEC...

Page 42: ...H 0 CLEAR INTERRUPT REQUEST FLAG 212 C06F E400F5 LDM IRQL 0 213 C072 E402F8 LDM IEDS 2 EXT INT 0 RISING EDGE SELECT 214 C075 E0 EI ENABLE INTERRUPT EOR Exclusive OR Function A A M Description Exclusive OR the accumulator and the contents of memory The result is left in the accumulator Flag Mnemonic OP Code Bytes Cycles EOR imm A4 2 2 EOR dp A5 2 3 EOR dp X A6 2 4 EOR abs A7 3 4 EOR abs Y B5 3 5 EO...

Page 43: ...BC AB2E20 EOR1 2EH 1 473 F8BF D004 BCS DIFE 474 F8C1 C400 LDA 0 475 F8C3 2F02 BRA UNIO 476 F8C5 C403 DIFE LDA 3 477 F8C7 FF UNIO NOP EOR1B Bit exclusive OR 1 s complement Function C C M bit Description Exclusive OR of the carry flag and 1 s complement of the specified bit of memory Flag Mnemonic OP Code Bytes Cycles EOR1B M bit AB 3 5 The bit4 of the 3rd byte is set to 1 Example 319 M_BIT0 EQU 0 C...

Page 44: ...CHCNT 385 C180 4414 CMP 20 386 C182 7003 BNE ADCC1 387 C184 E40015 LDM CHCNT 0 388 C187 C515 ADCC1 LDA CHCNT INCW Increment word 16 bit Function dp 1 dp dp 1 dp 1 Description Increment the contents of 16bit memory pair by 1 Flag Mnemonic OP Code Bytes Cycles INCW dp 9D 2 6 Example 504 C218 9D03 INCW DPL INCREMENT DPL 1 DPL 505 C21A C401 LDA 01H 506 C21C 4504 CMP DPH 507 C21E 70F3 BNE TXLP1 508 C22...

Page 45: ...13 F004 BEQ STPMOD 302 C115 20 CLRC 303 C116 1B0CC1 JMP LOOP LDA Load accumulator Function A M Description The accumulator is loaded with contents of specified memory or immediate data Flag Mnemonic OP Code Bytes Cycles LDA imm C4 2 2 LDA dp C5 2 3 LDA dp X C6 2 4 LDA abs C7 3 4 LDA abs Y D5 3 5 LDA dp X D6 2 6 LDA dp Y D7 2 6 LDA X D4 1 3 LDA X DB 1 4 Example 445 F894 C5C2 LDA 0C2H R2 PORT M 5CH ...

Page 46: ...40 LDC 0C0H 2 R02 CARRY 476 F8C0 AB2E20 EOR1 2EH 1 LDCB Load carry 1 s complement Function C M bit Description The carry flag is loaded with 1 s complement of the specified bit of memory Flag Mnemonic OP Code Bytes Cycles LDCB M bit CB 3 4 The bit4 of 3rd byte is set to 0 Example 379 C151 20 CLRC 380 C152 E4CC36 REPEAT2 LDM 36H 0CCH 381 C155 8936 INC 36H 382 C157 CB3630 LDCB 36H 1 383 C15A 50F6 BC...

Page 47: ... 492 C200 91C6 CLR1 CMDDAT 493 C202 C503 LDA DPL 494 C204 3B35C3 CALL LCDWR LDX Load X register Function X M Description The X register is loaded with contents of the specified memory or of the immediate data Flag Mnemonic OP Code Bytes Cycles LDX imm 1E 2 2 LDX dp CC 2 3 LDX dp Y CD 2 4 LDX abs DC 3 4 Example 421 C1B1 CC15 ADCON1 LDX CHCNT DATA STORE 422 C1B3 E617 STA ADCD0 X 423 C1B5 012F SET1 A...

Page 48: ...PORT 0FFH Segment All Turn Off 35 F01D CC21 LDX SEG_POINTER Segment Pattern Data Output 36 F01F D922 LDY SEG1 X 37 F021 D526F0 LDA FONT Y 38 F024 E5C4 STA LED_PORT 39 40 F026 C0 FONT DB 0C0H 0F9H 0A4H 0B0H 99H 92H 82H 0D8H 080H 090H F027 F9 F028 A4 F029 B0 F02A 99 F02B 92 F02C 82 F02D D8 F02E 80 F02F 90 LDYA Load YA 16bit accumulator Function YA dp 1 dp Description The 16 bit accumulator YA is loa...

Page 49: ...p X 59 2 5 LSR abs 58 3 5 Example 424 C183 C4FF LDA 0FFH 425 C185 E40808 LDM TEMP 8 426 C188 A908 LOOP3 DEC TEMP 427 C18A 48 LSR A 428 C18B 70FB BNE LOOP3 MUL Multiply Function YA Y A Description Multiply Y register by accumulator The result is left in the 16bit accumulator YA Flag Mnemonic OP Code Bytes Cycles MUL 5B 1 9 Example 624 C2E6 C517 ADCHK LDA ADCD0 625 C2E8 3E63 LDY 99 A D input 0 255 0...

Page 50: ...6 C119 20 STPMOD CLRC 307 C11A 00 STOP 308 C11B FF NOP 309 C11C FF NOP 310 C11D FF NOP 311 C120 1B00C0 JMP MAIN NOT1 Bit complement Function M bit M bit Description 1 s complement of the specified bit of memory Flag Mnemonic OP Code Bytes Cycles NOT1 M bit 4B 3 5 Example 109 F07C C5C0 LDA 0C0H 110 F07E E546 STA 46H 111 F080 4B4660 NOT1 46H 3 REVERSE BIT 46H 3 ...

Page 51: ...OR abs Y 75 3 5 OR dp X 76 2 6 OR dp Y 77 2 6 OR X 74 1 3 Example 458 C1A7 C4F0 LDA 0F0H 459 C1A9 E40F08 LDM TEMP 0FH 460 C1AC 6508 OR TEMP 461 C1AE E408C1 LDM R0DD TEMP OR1 Bit logical OR Function C C M bit Description Logical OR of the carry flag and the specified bit of memory The result is left in the carry flag Flag Mnemonic OP Code Bytes Cycles OR1 M bit 6B 3 5 Example 161 F0BC CB6020 LDC 60...

Page 52: ...166 F0C5 CB6020 LDC 60H 1 167 F0C8 6B7FF0 OR1B 7FH 7 168 F0CB EB7FF0 STC 7FH 7 7FH 7 60H 1 7FH 7 PCALL U Page call Function M SP PCH SP SP 1 M SP PCL SP SP 1 PCL upage PCH 0FFH Description Call subroutine within upage Flag Mnemonic OP Code Bytes Cycles PCALL upage 4F 2 6 Example 365 F195 4F00 PCALL DELAY USE 2 BYTE 366 F197 3B00FF CALL DELAY USE 3 BYTE 367 368 369 ORG 0FF00H PCALL AREA ADDRESS 370...

Page 53: ...P A RESTORE ACC PUSH Push to stack Function M SP Reg SP SP 1 Description Push the contents of operand A X Y PSW into stack Flag Mnemonic OP Code Bytes Cycles PUSH A 0E 1 4 PUSH X 2E 1 4 PUSH Y 4E 1 4 PUSH PSW 6E 1 4 Example 374 ADCC INTERRUPT ROUTINE 376 C172 0E PUSH A SAVE ALL REGISTERS AND PSW 377 C173 2E PUSH X 378 C174 4E PUSH Y 379 C175 6E PUSH PSW 380 C176 13E821 BBC ADSF ADCC3 CHECK PREVIOU...

Page 54: ...00 10 508 FF0D 3BF5C0 CALL BYE 509 SOUND3 510 FF10 A902 DEC TIMER_COUNT200 511 FF12 5115 CLR1 F_SOUND 512 FF14 E400D1 LDM PMR5 0 513 FF17 6F RET RETI Return from interrupt routine Function SP SP 1 PSW M SP SP SP 1 PCL M SP SP SP 1 PCH M SP Description Return from interrupt routine Flag restored Mnemonic OP Code Bytes Cycles RETI 7F 1 6 Example 273 E133 0E TIMERINT PUSH A SAVE ACC 274 E134 8929 INC...

Page 55: ...EFT 73 F054 A0 SETC 74 F055 2931 ROL 31H SHIFT LEFT 1 BIT 75 F057 2930 ROL 30H ROR Rotate right through carry Function 7 6 5 4 3 2 1 0 C Description Rotate the accumulator or the contents of memory to the right side by 1bit Move the carry flag to bit7 and bit0 enter into the carry flag Flag Mnemonic OP Code Bytes Cycles ROR A 68 1 2 ROR dp 69 2 4 ROR dp X 79 2 5 ROR abs 78 3 5 Example 282 E13A C90...

Page 56: ...dp X 26 2 4 SBC abs 27 3 4 SBC abs Y 35 3 5 SBC dp X 36 2 6 SBC dp Y 37 2 6 SBC X 34 1 3 Example 244 E117 A0 SETC 245 E118 C56E LDA DATA1 246 E11A 245F SBC 5FH DATA1 5FH DATA0 247 E11C E5A6 STA DATA0 SET1 Set bit Function dp bit 1 Description Set the specified bit of memory to 1 Flag Mnemonic OP Code Bytes Cycles SET1 dp bit x1 2 4 X means that the bit4 of op code is 0 Example 61 E03E C11F SET1 1F...

Page 57: ...ytes Cycles SETA1 A bit 0B 2 2 Example 319 E15D 0BA0 SETA1 A 5 320 E15F 2F02 BRA KOU3 321 E161 2B00 CLRA1 A 0 322 E163 FF KOU3 NOP SETC Set carry bit Function C 1 Description Set carry flag to 1 Flag 1 Mnemonic OP Code Bytes Cycles SETC A0 1 2 Example 216 E0FD A0 SETC 217 E0FE 2F01 BRA LPA6 218 E100 20 CLRC 219 E101 FF LPA6 NOP ...

Page 58: ...OM PAGE0 TO PAGE1 238 E117 40 CLRG 239 E118 E605 STA WORK0 X STA Store accumulator Function M A Description Store the contents of accumulator to memory Flag Mnemonic OP Code Bytes Cycles STA dp E5 2 4 STA dp X E6 2 5 STA abs E7 3 5 STA abs Y F5 3 6 STA dp X F6 2 7 STA dp Y F7 2 7 STA X F4 1 4 STA X FB 1 4 Example 339 F16B C400 LDA 0 340 F16D 0534 ADC 34H M 34H CY M 34 341 F16F E534 STA 34H ...

Page 59: ... 2F01 BRA RTN 354 F181 20 SETCY CLRC 355 F182 6F RTN RET STOP Stop mode Function halt CPU stop the oscillation Description Enter into the STOP mode Flag Mnemonic OP Code Bytes Cycles STOP 00 1 3 Example 359 F183 C530 LDA 30H 360 F185 4404 CMP 4 361 F187 7003 BNE 5 362 F189 1B18F1 JMP PROG 363 F18C 4403 CMP 3 364 F18E 7003 BNE 5 365 F190 1B4EF1 JMP PROGA 366 F193 4402 CMP 2 367 F195 7003 BNE 5 368 ...

Page 60: ...5 Example 396 F1A2 8F INC X 397 F1A3 EC29 STX POINTER STORE X REG INTO POINTER 398 F1A5 C67E LDA MODE X STY Store Y register Function M Y Description Store the contents of Y register to memory Flag Mnemonic OP Code Bytes Cycles STY dp E9 2 4 STY dp X F9 2 5 STY abs F8 3 5 Example 401 F1A7 BE DEC Y 402 F1A8 D5A2F1 LDA DATA_TBL Y 403 F1AB E97E STY MODE STORE Y REG INTO MODE 404 F1AD 445A CMP 5AH ...

Page 61: ...6A 1D40 ADDW 40H M 31H M 30H M 41H M 40H 410 F86C DD50 STYA 50H YA M 51H M 50H SUBW Subtract word without Carry Function YA YA dp 1 dp Description Subtract the contents of memory pair from 16 bit accumulator YA Flag Mnemonic OP Code Bytes Cycles SUBW dp 3D 2 5 Example 430 DATA_WORD DS 2 431 C16C E4AA18 LDM DATA_WORD 0AAH 432 C16F E43F19 LDM DATA_WORD 1 03FH 433 C172 C47F LDA 7FH 434 C174 3EEA LDY ...

Page 62: ...TAX E8 1 2 Example 441 C17A C464 LDA 100 442 C17C A8 LOOP0 DEC A 443 C17D 70FD BNE LOOP0 444 C17F E8 TAX TAY Transfer accumulator into Y register Function Y A Description Transfer the accumulator to Y register Flag Mnemonic OP Code Bytes Cycles TAY 9F 1 2 Example 449 C180 C411 LDA 11H 450 C182 3EAA LDY 0AAH 451 C184 E908 STY TEMP 452 C186 9F TAY 453 C187 C508 LDA TEMP ...

Page 63: ...E PUSH A 556 C1D2 2E PUSH X 557 C1D3 4E PUSH Y 558 559 C1D4 3A TCALL 3 560 561 ORG 0FFD8H 562 FFD8 D1C1 DW SAVE TCLR1 Test and clear bits with A Function A abs abs abs A Description Tests whether the contents of memory is A or lower than A According to the result the flag is effected Flag Mnemonic OP Code Bytes Cycles TCLR1 abs 5C 3 6 Example 459 C189 C420 LDA 20H 460 C18B E4FF35 LDM 0035H 0FFH 46...

Page 64: ...7 C193 E4FF30 LDM 0030H 0FFH 468 C196 3C3000 TSET1 0030H TSPX Transfer stack pointer into X register Function X SP Description Transfer the stack pointer to X Register Flag Mnemonic OP Code Bytes Cycles TSPX AE 1 2 Example 473 C199 3E30 LDY 30H 474 C19B C420 LDA 20H 475 C19D 1EFE LDX 0FEH 476 C19F 8E TXSP 477 C1A0 0E PUSH A 478 C1A1 2E PUSH X 479 C1A2 4E PUSH Y 480 C1A3 AE TSPX ...

Page 65: ...XA Transfer X register into accumulator Function A X Description Transfer the X register to the accumulator Flag Mnemonic OP Code Bytes Cycles TXA C8 1 2 Example 493 C1A9 1E64 LDX 100 494 C1AB AF LOOP1 DEC X 495 C1AC 70FD BNE LOOP1 496 C1AE C8 TXA 497 TXSP Transfer X register into stack pointer Function SP X Description Transfer the X register to the stack pointer Flag Mnemonic OP Code Bytes Cycle...

Page 66: ...B7 BF TYA XAX Exchange accumulator with X register Function X A Description Exchange the accumulator with the X register Flag Mnemonic OP Code Bytes Cycles XAX EE 1 4 Example 517 C1B8 C4AA LDA 0AAH 518 C1BA 1EFF LDX 0FFH 519 C1BC EE XAX XAY Exchange accumulator with Y register Function Y A Description Exchange the accumulator with the Y register Flag Mnemonic OP Code Bytes Cycles XAY DE 1 4 Exampl...

Page 67: ...lator Function M A Description Exchange the accumulator with the contents of memory Flag Mnemonic OP Code Bytes Cycles XMA dp BC 2 5 XMA dp X AD 2 6 XMA X BB 1 5 Example 539 C1C5 E4F008 LDM TEMP 11110000B 540 C1C8 C40F LDA 00001111B 541 C1CA BC08 XMA TEMP XYX Exchange Y register with X register Function X Y Description Exchange the Y Register with the X Register Flag Mnemonic OP Code Bytes Cycles ...

Page 68: ...HYUNDAI MicroElectonics 64 ...

Page 69: ...111 EI LDM dp imm STA dp STA dp X STA abs TAX STY dp TCALL 14 STC M bit STX dp STX dp Y XAX LOW HIGH 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1A 11011 1B 11100 1C 11101 1D 11110 1E 11111 1F 000 BPL rel CLR1 dp bit BBC A bit rel BBC dp bit rel ADC X ADC abs Y ADC dp X ADC dp Y ASL abs ASL dp X TCALL 1 JMP abs BIT abs ADDW dp LDX imm JMP abs 001...

Page 70: ...L abs 18 3 5 24 BBC A bit rel y2 2 4 6 Branch if bit clear 25 BBC dp bit rel y3 3 5 7 if bit 0 then PC PC rel 26 BBS A bit rel x2 2 4 6 Branch if bit set 27 BBS dp bit rel x3 3 5 7 if bit 1 then PC PC rel 28 BCC rel 50 2 2 4 Branch if carry bit clear if C 0 then PC PC rel 29 BCS rel D0 2 2 4 Branch if carry bit set if C 1 then PC PC rel 30 BEQ rel D0 2 2 4 Branch if equal if Z 1 then PC PC rel 31 ...

Page 71: ...P dp Y 57 2 6 56 CMP X 54 1 3 57 CMPW dp 5D 2 4 Compare YA contents with memory pair contents YA dp 1 dp N ZC 58 CMPX imm 5E 2 2 Compare X contents with memory contents 59 CMPX dp 6C 2 3 X M N ZC 60 CMPX abs 7C 3 4 61 CMPY imm 7E 2 2 Compare Y contents with memory contents 62 CMPY dp 8C 2 3 Y M N ZC 63 CMPY abs 9C 3 4 64 COM dp 2C 2 4 1 s Complement dp dp N Z 65 DAA DF 1 3 Decimal adjust for addit...

Page 72: ...jump 97 JMP abs 1F 3 5 PC jump address 98 JMP dp 3F 2 4 99 LDA imm C4 2 2 Load accumulator 100 LDA dp C5 2 3 A M 101 LDA dp X C6 2 4 102 LDA abs C7 3 4 103 LDA abs Y D5 3 5 N Z 104 LDA dp X D6 2 6 105 LDA dp Y D7 2 6 106 LDA X D4 1 3 107 LDA X DB 1 4 X register auto increment A M X X 1 108 LDC M bit CB 3 4 Load C flag C M bit C 109 LDCB M bit CB 3 4 Load C flag with NOT C M bit C 110 LDM dp imm E4...

Page 73: ... 2D 1 4 SP SP 1 Reg M SP 140 POP Y 4D 1 4 141 POP PSW 6D 1 4 restored 142 PUSH A 0E 1 4 Push to stack 143 PUSH X 2E 1 4 M SP Reg SP SP 1 144 PUSH Y 4E 1 4 145 PUSH PSW 6E 1 4 146 RET 6F 1 5 Return from subroutine SP SP 1 PCL M SP SP SP 1 PCH M SP 147 RETI 7F 1 6 Return from interrupt SP SP 1 PSW M SP SP SP 1 PCL M SP SP SP 1 PCH M SP restored 148 ROL A 28 1 2 Rotate left through carry 149 ROL dp 2...

Page 74: ...X E8 1 2 Transfer accumulator contents to X register X A N Z 187 TAY 9F 1 2 Transfer accumulator contents to Y register Y A N Z 188 TCALL n nA 1 8 Table call M SP PCH SP SP 1 M SP PCL SP SP 1 PCL Table vector L PCH Table vector H 189 TCLR1 abs 5C 3 6 Test and clear bits with A A M M M A N Z 190 TSET1 abs 3C 3 6 Test and set bits with A A M M M A N Z 191 TSPX AE 1 2 Transfer stack pointer contents ...

Page 75: ... ASL dp X 19 2 5 20 ASL abs 18 3 5 21 CMP imm 44 2 2 Compare accumulator contents with memory contents 22 CMP dp 45 2 3 A M 23 CMP dp X 46 2 4 24 CMP abs 47 3 4 N ZC 25 CMP abs Y 55 3 5 26 CMP dp X 56 2 6 27 CMP dp Y 57 2 6 28 CMP X 54 1 3 29 CMPX imm 5E 2 2 Compare X contents with memory contents 30 CMPX dp 6C 2 3 X M N ZC 31 CMPX abs 7C 3 4 32 CMPY imm 7E 2 2 Compare Y contents with memory conte...

Page 76: ...A N Z 64 OR imm 64 2 2 Logical OR 65 OR dp 65 2 3 A A M 66 OR dp X 66 2 4 67 OR abs 67 3 4 N Z 68 OR abs Y 75 3 5 69 OR dp X 76 2 6 70 OR dp Y 77 2 6 71 OR X 74 1 3 72 ROL A 28 1 2 Rotate left through carry 73 ROL dp 29 2 4 C 7 6 5 4 3 2 1 0 N ZC 74 ROL dp X 39 2 5 75 ROL abs 38 3 5 76 ROR A 68 1 2 Rotate right through carry 77 ROR dp 69 2 4 7 6 5 4 3 2 1 0 C N ZC 78 ROR dp X 79 2 5 79 ROR abs 78 ...

Page 77: ...26 STA X FB 1 4 X register auto increment M A X X 1 27 STX dp EC 2 4 Store X register contents in memory 28 STX dp Y ED 2 5 M X 29 STX abs FC 3 5 30 STY dp E9 2 4 Store Y register contents in memory 31 STY dp X F9 2 5 M Y 32 STY abs F8 3 5 33 TAX E8 1 2 Transfer accumulator contents to X register X A N Z 34 TAY 9F 1 2 Transfer accumulator contents to Y register Y A N Z 35 TSPX AE 1 2 Transfer stac...

Page 78: ... 2 4 Bit test A with memory MM Z 4 BIT abs 1C 3 5 Z A M N M7 V M6 5 CLR1 dp bit y1 2 4 Clear bit M bit 0 6 CLRA1 A bit 2B 2 2 Clear A bit A bit 0 7 CLRC 20 1 2 Clear C flag C 0 0 8 CLRG 40 1 2 Clear G flag G 0 0 9 CLRV 80 1 2 Clear V flag V 0 0 0 10 EOR1 M bit AB 3 5 Bit exclusive OR C flag C C M bit C 11 EOR1B M bit AB 3 5 Bit exclusive OR C flag and NOT C C M bit C 12 LDC M bit CB 3 4 Load C fla...

Page 79: ...minus if N 0 then PC PC rel 11 BRA rel 2F 2 4 Branch always PC PC rel 12 BVC rel 30 2 2 4 Branch if overflow bit clear if V 0 then PC PC rel 13 BVS rel B0 2 2 4 Branch if overflow bit set if V 1 then PC PC rel 14 CALL abs 3B 3 8 Subroutine call 15 CALL dp 5F 2 8 M SP PCH SP SP 1 M SP PCL SP SP 1 if abs PC abs if dp PCL dp PCH dp 1 16 CBNE dp rel FD 3 5 7 Compare and branch if not equal 17 CBNE dp ...

Page 80: ...P FF 1 2 No operation 5 POP A 0D 1 4 SP SP 1 A M SP 6 POP X 2D 1 4 SP SP 1 X M SP 7 POP Y 4D 1 4 SP SP 1 Y M SP 8 POP PSW 6D 1 4 SP SP 1 PSW M SP restored 9 PUSH A 0E 1 4 M SP A SP SP 1 10 PUSH X 2E 1 4 M SP X SP SP 1 11 PUSH Y 4E 1 4 M SP Y SP SP 1 12 PUSH PSW 6E 1 4 M SP PSW SP SP 1 13 RET 6F 1 5 Return from subroutine SP SP 1 PCL M SP SP SP 1 PCH M SP 14 RETI 7F 1 6 Return from interrupt SP SP ...

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