Hughes JVC 220, Service Manual

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Chapter 2---System Description
+5.1V_STBY Stand by + 5.1 V. Not used by RTG board.
Interlock and protection:
Input
None
Output
The RTG will disable the Horizontal Deflection Board by placing a
high on the /H_ENABLE line during any of following events:
A. During and about 2 seconds after the programming period of
the FPGA.
B. During frequency band change period.
C. During the period that the phase locked loop is out of lock.
2.3.8 Horizontal/Vertical Deflection PCB
The HVD board is located on the top side of the deflection cage in
front of the electronic card cage.
The Horizontal/Vertical Deflection Board I/O diagram (Figure 2-14)
and the list of inputs and outputs (Tables 2-14 and 2-15) provide
information for the technician to perform module level
troubleshooting.
The following functions are provided by the HVD board:
•
Horizontal raster centering for all three colors
•
Horizontal gate drive
•
Switch mode power supply generating the required
proportional DC supply
•
Horizontal width adjustment
•
Horizontal retrace switch network
•
Left/right pincushion and keystone correction
•
Drive main deflection coils to provide horizontal raster scan for
all three CRTs
•
Drive main vertical coils to provide vertical raster scan for all
three CRTs
•
Vertical linearity adjustments individually for all three colors.
•
Vertical raster centering for all three colors
•
IIC interface
IIC Interface
All adjustments for the HVD board are performed by the System
Controller via the IIC serial bus interface. This three wire bus
Model 220 Service Manual 2-43