HUAWEI MU509-65 HSDPA LGA Module
Hardware Guide
Description of the Application Interfaces
Issue 01 (2016-04-08)
Huawei Proprietary and Confidential
Copyright © Huawei Technologies Co., Ltd.
41
Figure 3-23
Circuit diagram of the interface of the PCM (MU509-65 is used as PCM
master)
It is recommended that a TVS be used on the related interface, to prevent electrostatic
discharge and protect integrated circuit (IC) components.
3.9 General Purpose I/O Interface
The module provides 8 GPIO pins for customers to use for controlling signals which
are worked at 2.6 V CMOS logic levels. Customers can use AT command to control
the state of logic levels of eight channels GPIO output signal, see the
HUAWEI
MU509-65 HSDPA LGA Module AT Command Interface Specification
.
Table 3-13
Signals on the GPIO interface
Pin No.
Pin
Name
Pad
Type
Description
Parameter
Min.
(V)
Typ.
(V)
Max.
(V)
Comments
44, 45,
46, 51,
55, 105,
109 and
113
GPIO
I/O
General
Purpose I/O
pin
V
OH
2.15
2.6
2.6
The
function of
these pins
has not
been
defined.
V
OL
0
-
0.45
V
IH
1.69
2.6
2.9
V
IL
–0.3
-
0.91
3.10 JTAG Interface
The MU509-65 module provides one JTAG (Joint Test Action Group) interface. It is
suggested that place the follow test points in the DTE board for debug and take ESD
