15
Internal circuit of Line0
Figure 3-21
The maximum output current of Line0 is 25 mA.
The pull-up resistance value complies with the maximum allowed current of the opto-isolated
output port under the defined voltage.The larger the resistance value, the smaller the optocoupler
forward voltage drop, the more slowly the output wave changes and the weaker the ability to
power external devices. The recommended optocoupler value is 270 Ω, 560 Ω and 1 kΩ when the
voltage is 5 V, 12 V and 24 V respectively.
The rising and falling time, delay time of rising and falling edge are shown as Figure 3-22 when the
pull-up voltage is 1 kΩ.
Delay time of rising and falling
Figure 3-22
The electrical specifications of the opto-isolated output are shown in below table Table 3-4 when
the external voltage is 3.3 V and resistance is 1 kΩ.
Table 3-4
Output trigger time
External
Voltage (V)
Rising Time
t
R
(us)
Falling Time
t
F
(us)
Rising Edge
Trigger Delay tDR
(us)
Falling Edge Trigger
Delay tDF (us)
5
19.70
3.20
39.9
8.06
12
24.06
5.22
44.8
11.8
24
30.11
8.10
44.8
53.2
The optocoupler output delay is the time delay from FPGA internal logic output to external
opto-isolated output pin.
Rising edge trigger delay is the time delay from the 10% of the FPGA pin output level to the 90%
of the external output signal amplitude.
Falling edge trigger delay is the time delay from the 90% of the FPGA pin output level to the
10% of the external output signal amplitude.
Rising time is the time delay from the 10% of the external output signal amplitude to 90%.
Falling time is the time delay from the 90% of the external output signal amplitude to 10%.
