HP ProLiant BL620c G7, User Manual

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Hardware options installation 38
Item Description Definition
6
DIMM type R = RDIMM (registered)
E = UDIMM (unbuffered with ECC)
For the latest supported memory information, see the QuickSpecs on the HP website ( http://www.hp.com ).
DIMM installation guidelines
Each supported processor contains two memory controllers per processor. Each memory controller can
support up to eight DDR3 registered 1.5V DIMMs (RDIMMs) and 1.35V low voltage DIMMs (LV DIMMs). LV
DIMM support is limited to HP ProLiant BL620c G6 Server Blade models that support the Intel® Xeon® E7
processors. Four memory controllers across two processors provide a total of 32 DIMMs per system.
When installing DIMMs, observe the following minimum guidelines:
•
Install only HP DDR3-1333 DIMMs supported by the server blade.
•
DIMMs must be installed for processor 1.
•
Populate DIMM slots for a processor only if the processor is installed.
•
To maximize performance in multi-processor configurations, distribute the total memory capacity
between all processors as evenly as possible.
•
The minimum configuration is two DIMMs installed on processor 1.
•
DIMMs must be installed in pairs with identical characteristics. When possible, for configuration
simplicity, HP recommends using DIMMs with identical part numbers throughout the system.
•
No special socket requirements exist for regular 1.5V DIMMs and 1.35V LV DIMMs. If both 1.5V
DIMMs and 1.35V LV DIMMs are used in the same system, all DIMMs operate at 1.5V.
•
For best performance, HP recommends that DIMM pairs be populated in sequence by letter
designation. Install DIMM pair 4A/5A first, followed by DIMM pair 12B/16B, DIMM pair 2C/7C,
DIMM pair 10D/14D, DIMM pair 3E/6E, DIMM pair 11F/15F, and DIMM pair 1G/8G.
•
When installing mixed rank DIMMs for any processor, DIMMs with the highest number of ranks must be
installed in the white DIMM connector locations. This guarantees proper electrical signaling on the
DDR3 channel since DIMMs with higher rank counts present larger electrical loading on the DDR3
channel and must be populated at the end point of the channel.
CAUTION: Failure to follow these guidelines may result in the inability to recognize memory,
memory errors, or reduced memory performance.
Examples:
o
If the configuration is eight quad-rank 8-GB DIMMs and eight dual-rank 8-GB DIMMs installed in a
single-processor configuration, the quad-rank DIMMs must be installed in the white DIMM
connectors 4A/5A, 12B/16B, 2C/7C, and 10D/14D. The dual-rank DIMMs must be installed in
the black DIMM connectors 3E/6E, 11F/15F, 1G/8G, and 9H/13H. For illustrations of the
connections between the processor, memory controllers, and DIMMs, see "Memory subsystem
architecture (on page
39 )."
o
If the configuration is six quad-rank 8-GB DIMMs and ten dual-rank 8-GB DIMMs in a single
processor configuration, the quad-rank DIMMs can be located in any of the corresponding white
DIMM pairs (4A/5A, 12B/16B, 2C/7C, and 10D/14D), as long as they are installed at the end
point of the DDR3 channel.