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HP E1459A SCPI Command Reference

STATus:QUEStionable:CONDition?

Always returns a 0.

Note

The Questionable Status Condition, Event, and Enable registers exist for SCPI
compliance only. No status bits are defined or reported in these registers.

Parameters

None

Comments

•

No bits are defined.

•

*RST clears all Status Questionable Conditions.

•

*CLS does not affect the contents of the Status Questionable Conditions.

•

The STAT:PRESet command does not affect the Status Questionable

Conditions.

STATus:QUEStionable:ENABle <

mask

>

Sets the value of the QUEStionable Status Enable Register.

Note

The Questionable Status Condition, Event, and Enable registers exist for SCPI
compliance only. No status bits are defined or reported in these registers.

Parameters

None

Comments

•

No bits are defined.

•

*RST and *CLS do not affect the value of the enable mask.

•

The STAT:PRESet command sets the value of the enable mask to 0.

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Summary of Contents for E1459A

Page 1: ...tions 18 Interrupt Parsing 18 Configuring for Installation 19 Setting the Logical Address 20 Setting the Interrupt Priority 20 Setting Input Threshold Levels 21 Setting the Reset Time on the Watchdog Timer 21 Connecting User Inputs 22 Installing the HP E1459A in a VXIbus Mainframe 24 Terminal Block 25 Wiring a Terminal Block 26 Chapter 2 Using the HP E1459A Module 29 Power on Reset States 30 Examp...

Page 2: ...n type BITm 50 MEMory Subsystem 51 MEMory DELete MACRo name 51 SENSe Subsystem 52 SENSe EVENt PORTn DAVailable 52 SENSe EVENt PORTn DAVailable ENABle state 53 SENSe EVENt PORTn DAVailable ENABle 53 SENSe EVENt PORTn EDGE 54 SENSe EVENt PORTn EDGE ENABle state 54 SENSe EVENt PORTn EDGE ENABle 55 SENSe EVENt PORTn NEDGe 55 SENSe EVENt PORTn NEDGe ENABle mask 56 SENSe EVENt PORTn NEDGe ENABle 56 SENS...

Page 3: ...gister 78 Edge Interrupt Status Register 80 Data Available Status Register 80 Watchdog Timer Control Status Register 81 Command Register Port 0 2 81 Channel Data Register Port 0 2 83 Positive Edge Detect Register Port 0 2 83 Negative Edge Detect Register Port 0 2 84 Positive Mask Register Port 0 2 84 Negative Mask Register Port 0 2 84 Debounce Clock Register Port 0 and Port1 Port 2 and Port 3 85 C...

Page 4: ...4 Contents ...

Page 5: ...alfunctions of HP products that result from the Buyer s circuitry In addition HP does not warrant any damage that occurs as a result of the Buyer s circuit or any defects that result from Buyer supplied products NO OTHER WARRANTY IS EXPRESSED OR IMPLIED HP SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Exclusive Remedies THE REMEDIES PROVIDED ...

Page 6: ...ort circuited fuse holders Keep away from live circuits Operating personnel must not remove equipment covers or shields Procedures involving the removal of covers or shields are for use by service trained personnel only Under certain conditions dangerous voltages may exist even with the equipment switched off To avoid dangerous electrical shock DO NOT perform procedures involving cover or shield r...

Page 7: ... following Product Specifications Safety IEC 1010 1 1990 Incl Amend 1 1992 EN61010 1 A2 1995 CSA C22 2 1010 1 1992 UL 3111 EMC CISPR 11 1990 EN55011 1991 Group1 Class A EN50082 1 1992 IEC 801 2 1991 4kVCD 8kVAD IEC 801 3 1984 3 V m IEC 801 4 1988 1kV Power Line ENV50141 1993 prEN50082 1 1995 3Vrms ENV50142 1994 prEN50082 1 1995 1kV CM 0 5kV DM IEC1000 4 8 1993 prEN50082 1 1995 3A m EN61000 4 11 19...

Page 8: ...8 Notes ...

Page 9: ...rea Code Please list the system controller operating system programming language and plug in modules you are using BUSINESS REPLY MAIL FIRST CLASS PERMIT NO 37 LOVELAND CO POSTAGE WILL BE PAID BY ADDRESSEE HEWLETT PACKARD COMPANY Measurement Systems Division Learning Products Department P O Box 301 Loveland CO 80539 9984 fold here Please pencil in one circle for each statement below Disagree Agree...

Page 10: ......

Page 11: ...d or negative edge transition Channel inputs are also debounced to help prevent erroneous transition detection on noisy signals Two programmable clock sources control the debounce circuitry one for ports 0 and 1 one for ports 2 and 3 1 The HP E1459A and Z2404B are functionally identical The HP E1459A is provided with a downloadable SCPI driver and a VXIplug play driver the HP Z2404B was not provid...

Page 12: ...12 Installing and Configuring the HP E1459A Figure 1 1 HP E1459A 64 Channel Isolated Digital Input Interrupt Block Diagram To VXIbus Transceivers ...

Page 13: ...king technique data channels may function as edge detect inputs and or data capture inputs Events at any channel may occur simultaneously or in overlap with events on any other channel Figure 1 2 is a block diagram of the hardware interrupt resolver circuit User software algorithms are also necessary to resolve issues of overlap and to determine the occurring sequence of events Figure 1 2 Resolver...

Page 14: ...ers Debounce circuits require that a channel input remain in a stable state for 4 to 4 5 periods of the programmable clock before a channel transition is declared The debounce clocks may be programmed for frequencies ranging from 250 KHz down to 466 µHz The 4 to 4 5 clock period requirements of the debouncers translate into debounce periods which range from 16 µS minimum to 9600 seconds 2 67 hours...

Page 15: ... its channel group The static state of these markers may be tested via the Edge Interrupt Status Register These markers are also accessible at the front panel Caution Edge Detect Markers are cleared by a read of the register causing the marker to be posted Since there is no high level method of determining whether a positive or negative edge event is generating the marker both edge detect register...

Page 16: ...detected and the events are marked user software first reads the positive edge detect register and then the negative edge detect register Figure 1 3 Positive and Negative Edge Transitions In Figure 1 4 a channel that has been programmed for data capture posts a marker on the occurrence of an external capture clock During the subsequent data register read cycle another data capture clock occurs to ...

Page 17: ...event the marker bit is forced inactive for a two clock 16 MHz period before again being posted to the control FPGA In the Data Capture Mode the HP E1459A may be programmed to generate an interrupt on the occurrence of an external capture clock or an internal 1 0 MHz sample clock may be selected to allow the state of the data channels to be tested in the absence of a capture clock Capture clock se...

Page 18: ...sharing the same IRQ line some method is necessary to ensure that only a single IRQ is posted by the HP E1459A during each service interval Individual interrupts must be serviced by a commander on a one for one basis The HP E1459A accomplishes this by inhibiting the generation of a second IRQ each time an IRQ is posted THE INHIBIT CONDITION IS CLEARED BY THE REMOVAL AND REASSERTION OF EITHER INTER...

Page 19: ...user wiring connected to the terminal module consider the highest voltage present accessible on any terminal WARNING SHOCK HAZARD Use wire with an insulation rating greater than the highest voltage which will be present on the terminal module Do not touch any circuit element connected to the terminal module if any other connector to the terminal module is energized to more than 30 Vac RMS or 60 Vd...

Page 20: ...riority jumper selects which priority level will be asserted As shipped from the factory the interrupt priority jumper should be in position 1 In most applications this should not be changed When set to level X interrupts are disabled The interrupt priority jumpers are identified on the sheet metal shield A hole has been cut into the shield for access to the jumpers Interrupts can also be disabled...

Page 21: ...eset Time on the Watchdog Timer There are 2 jumpers located on the PC board used to control the reset time of the Watchdog Timer see Figure 1 6 The reset time is the maximum allowed time between accesses to keep the Watchdog from asserting SYSRESET The Watchdog timer is reset by reading the Watchdog Control Status register use the DIAG SYSR STAT command see Chapter 3 The following table shows the ...

Page 22: ...al It must also meet the drive requirements for the voltage threshold selected For each block of 16 channels an additional active low input and two active low outputs are available The table below lists the signal names and the associated channels Figure 1 7 shows the front panel terminals and pinouts for the module The cover to the terminal module is silk screened to indicate the function of each...

Page 23: ...27 LO 7 CH 28 HI CH 28 LO 6 CH 29 HI CH 29 LO 5 CH 30 HI CH 30 LO 4 CH 31 HI CH 31 LO 3 CH 32 HI CH 32 LO 2 CH 33 HI CH 33 LO 1 CH 34 HI CH 34 LO A B C 32 CH 35 HI CH 35 LO 31 CH 36 HI CH 37 LO CH 36 LO 30 CH 37 HI CH 38 LO 29 CH 38 HI CH 39 HI CH 39 LO 28 CH 40 HI CH 40 LO 27 CH 41 HI CH 42 LO CH 41 LO 26 CH 42 HI CH 43 LO 25 CH 43 HI CH 44 HI CH 44 LO 24 CH 45 HI CH 45 LO 23 CH 46 HI CH 46 LO 22...

Page 24: ...ers out 2 Slide the into any slot except slot 0 until the backplane connectors touch 3 Seat the into the mainframe by pushing in the extraction levers Extraction Levers 4 Tighten the top and bottom screws to secure the module to the mainframe To remove the from the mainframe reverse the procedure NOTE The extraction levers will not seat the backplane connectors on older VXIbus mainframes You must ...

Page 25: ... Maximum terminal wire size is No 16 AWG When wiring all channels a smaller gauge wire No 20 or 22 AWG is recommended Wire ends should be stripped 5 to 6 mm 0 2 to 0 25 in and tinned to prevent single strands from shorting to adjacent terminals WARNING To prevent the spread of fire in the case of a fault use flame rated field wiring whenever the input voltage will exceed 30Vrms 42Vpeak or 60Vdc CH...

Page 26: ...26 Installing and Configuring the HP E1459A Wiring a Terminal Block The following illustrations show how to connect field wiring to the terminal block Continued on Next Page ...

Page 27: ...r wire exit Keep wiring exit panel hole as small as possible 6 Replace Clear Cover A Hook in the top cover tabs onto the fixture B Press down and tighten screws 7 Install the Terminal Module HP E1459A Module 8 Push in the Extraction Levers to Lock the Terminal Module onto the HP E1459A Extraction Levers ...

Page 28: ...28 Installing and Configuring the HP E1459A ...

Page 29: ...ay driver do not do register writes This is because the high level driver will not know the instrument state and an interrupt may occur causing the driver and or command module to fail The example programs in this chapter were developed with the ANSI C language using the HP VISA extensions For additional information refer to the HP VISA User s Guide These programs were written and tested in Micros...

Page 30: ...s the ID string Created in Microsoft Visual C include visa h include stdio h include stdlib h define INSTR_ADDR GPIB0 9 3 INSTR HP E1459A logical address int main ViStatus errStatus status from VISA call ViSession viRM Resource Mgr session ViSession E1459 session for HP E1459A char id_string 256 0 ID string buffer char selftst_string 256 0 Open a default Resource Manager errStatus viOpenDefaultRM ...

Page 31: ..._string Query the ID string errStatus viQueryf E1459 IDN n t id_string if VI_SUCCESS errStatus printf ERROR viQueryf returned 0x x n errStatus return errStatus printf IDN returned s n id_string Close Sessions errStatus viClose E1459 if VI_SUCCESS errStatus printf ERROR viClose returned 0x x n errStatus return 0 errStatusviClose viRM if VI_SUCCESS errStatus printf ERROR viClose returned 0x x n errS...

Page 32: ... low a 1 in any bit position indicates the input to the corresponding channel is high Digital Input Example This program reads the current value of Port 0 16 bit word and combined value of Ports 2 and 3 32 bit word Created in Microsoft Visual C include visa h include stdio h include stdlib h define INSTR_ADDR GPIB0 9 3 INSTR HP E1459A logical address int main ViStatus errStatus status from VISA ca...

Page 33: ...Status printf ERROR viQueryf returned 0x x n errStatus return errStatus printf Value returned i n val1 Close Sessions errStatus viClose E1459 if VI_SUCCESS errStatus printf ERROR viClose returned 0x x n errStatus return 0 errStatus viClose viRM if VI_SUCCESS errStatus printf ERROR viClose returned 0x x n errStatus return 0 End of main program ...

Page 34: ...ailable Events until an event occurs Example 3 in this chapter demonstrates this procedure Polling the Status Subsystem The second method is to set up and repeatedly poll the Status Subsystem You can poll the port summary condition register with the STATus OPERation PSUMmary CONDition command to determine when an event has occurred Alternately set up the port summary enable register to specify the...

Page 35: ...mary Register 2 Poll the Status Subsystem 3 Use SRQ to interrupt Read the data and clear the event detector register SENSe EVENt PORTn NEDGE ENABle mask SENSe EVENt PORTn PEDGE ENABle mask INPutn DEBounce TIMe time SENSe EVENt PORTn EDGE ENABle state SENSe EVENt PSUMmary EDGe STATus OPERation PSUMmary CONDition STATus OPERation PSUMmary ENABle mask STATus OPERation ENABle 512 SRE128 SENSe EVENt PO...

Page 36: ... Subsystem 3 Use SRQ to interrupt INPutn DEBounce TIMe time SENSe EVENt PORTn DAVailable ENABle state Set External Clock Source INPutn CLOCk SOURce EXT SENSe EVENt PSUMmary DAV STATus OPERation PSUMmary CONDition STATus OPERation PSUMmary ENABle mask STATus OPERation ENABle 512 SRE128 HP E1459A Data Available Event Detection Flowchart Read the data and clear the event detector register MEASure DIG...

Page 37: ...current value Created in Microsoft Visual C include visa h include stdio h include stdlib h define INSTR_ADDR GPIB0 9 3 INSTR HP E1459A logical address int main ViStatus errStatus status from VISA call ViSession viRM Resource Mgr session ViSession E1459 session for HP E1459A int val event Open a default Resource Manager errStatus viOpenDefaultRM viRM if VI_SUCCESS errStatus printf ERROR viOpen ret...

Page 38: ...EDGE register and clear event detector register errStatus viQueryf E1459 EVEN PORT0 NEDGE n t val if VI_SUCCESS errStatus printf ERROR viPrintf returned 0x x n errStatus return errStatus printf Negative Edge Event value s n val Read PEDGE register and clear event detector register errStatus viQueryf E1459 EVEN PORT0 PEDGE n t val if VI_SUCCESS errStatus printf ERROR viPrintf returned 0x x n errSta...

Page 39: ...easurements querying instrument states or retrieving data A command subsystem structure is a hierarchical structure that usually consists of a top level or root command one or more low level commands and their parameters The following example shows the root command DISPlay and some of its lower level subsystem commands DISPlay MONitor PORT port PORT MINimum MAXimum DEFault STATe state STATe DISPla...

Page 40: ...t part of the command and are not sent to the instrument If you do not specify a value for an optional parameter the instrument chooses a default value For example consider the PORT MIN MAX command If you send the command without specifying a MINimum or MAXimum parameter the present PORT value is returned If you send the MIN parameter the command returns the minimum current display channel If you ...

Page 41: ...chdog Timer If the Watchdog timer is enabled the state of the timer MUST be read before the Watchdog time elapses If the state is not read before the time elapses the Watchdog Timer asserts the VXIbus SYSRESET line DIAGnostic SYSReset ENABle state Turns the Watchdog Timer ON or OFF Parameters Comments A 0 or OFF turns the Watchdog Timer off a 1 or ON turns the Timer on CAUTION When the Watchdog Ti...

Page 42: ...ommand Reference DIAGnostic SYSReset ENABle Returns the state of the Watchdog Timer as either a unsigned 1 or 0 Parameters None Comments Returns a 1 if the Watchdog Timer is enabled Returns a 0 if the Timer is not enabled ...

Page 43: ... PORT AUTO page 44 STATe state page 45 STATe page 45 DISPlay MONitor PORT port Sets the value of the DISPlay MONitor PORT or sets the automatic display mode Parameters Comments Sets the value of the Display Monitor to Port 0 1 2 or 3 AUTO automatically displays the results of a MEAS DIG DATAn command whenever that command is executed for the monitored Port if the display monitor is active for the ...

Page 44: ...TO state Sets the automatic mode for the Display Monitor on or off When AUTO mode is ON the port being monitored is automatically set to the last last port measured Parameters Comments a 0 or OFF turns the display monitor automatic mode off a 1 or ON turns the display monitor automatic mode on RST Condition sets the automatic mode on Example DISP MON PORT AUTO ON Turns automatic display mode on DI...

Page 45: ... Size of the data 16 bit word or 32 bit word Actual data signed decimal and hexadecimal A keyboard entry at the terminal sets DISP MON OFF RST Condition OFF Example DISP MON ON turns the display mode on DISPlay MONitor STATe Returns the value of the Display Monitor State as either 0 for OFF or 1 for ON Parameters None Comments DISP MON STAT returns a 1 if the monitor mode is on or returns a 0 if t...

Page 46: ...automatically clocked into the input debounce circuitry for each clock pulse of the internal clock when the clock source is INTernal Refer to the INPut DEBounce TIME command to set the Debounce time For a clock source of EXTernal new data is clocked into the input circuitry when the external clock receives a clock pulse Data is clocked into the input circuitry on the positive edge of the external ...

Page 47: ... 8 S 75 0 S 150 0 S 300 S 600 S 1200 S 2400 S 4800 S 9600 S Any value sent other than those listed is rounded to the nearest discrete value Debounce time is rounded to the nearest discrete value For example 16 0 µS to 18 4 µS is rounded to 18 µS 18 5 µS to 36 4 µS is rounded to 36 µS 36 5 µS to 72 4 µS is rounded to 72 µS etc Ports 0 and 1 use the same debounce time Ports 2 and 3 use the same debo...

Page 48: ...me debounce time For n 0 or n 1 this command returns the debounce time for both Ports 0 and 1 for n 2 or n 3 this command returns the debounce time for both Ports both Ports 2 and 3 Example INP2 DEB TIME Queries input circuit debounce time of Port 2 Parameter Name Parameter Type Range of Values Default INPutn time DEFault MINimum MAXimum numeric numeric floating pt 0 1 2 3 18 0 µsec through 9600 s...

Page 49: ...Parameters Comments For TYPE WORD the data is returned as a signed 16 bit integer Example values returned include 0 1 32767 32768 Specify port as either DATA0 DATA1 DATA2 or DATA3 For TYPE LWORd the data is returned as a signed 32 bit integer with Port 0 or Port 2 in the least significant bytes Specify port as DATA0 or DATA2 Default is Port 0 DATA is equivalent to DATA0 Example MEAS DIG DATA 1 WOR...

Page 50: ...st significant bits such that bit 0 of Port 2 becomes bit 0 and bit 15 of Port 3 becomes bit 31 of the 32 bit integer The specified Port must be DATA0 or DATA2 Refer to Chapter 2 for more details RST Condition sets the input clock source to INTernal and the debounce time to 18 0 µS Example MEAS DIG DATA3 WORD BIT 12 Queries value of Bit 12 in 16 bit word from Port 3 MEAS DIG DATA 2 LWORD BIT23 Que...

Page 51: ...s previously defined using the DMC Common Command The maximum length for name is 12 characters This command deletes the single named macro the PMC Common command purges all macros Example MEM DEL MACR test_macro Deletes the macro named test_macro which was previously defined using the DMC Common command Parameter Name Parameter Type Range of Values Default name discrete up to 12 alphanumeric chara...

Page 52: ...age 53 PORTn EDGE page 54 PORTn EDGE ENABle state page 54 PORT EDGE ENABle page 55 PORTn NEDG page 55 PORTn NEDG ENABle mask page 56 PORTn NEDG ENABle page 56 PORTn PEDG page 57 PORTn PEDG ENABle mask page 57 PORTn PEDG ENABle page 58 PSUMmary DAVailable page 58 PSUMmary EDGE page 59 SENSe EVENt PORTn DAVailable Returns the status of the DAVailable Event for Port n as either a unsigned 0 or a 1 Pa...

Page 53: ...CLOCk SOURce EXT command RST Condition disables the interrupt Example EVEN PORT 1 DAV ENAB ON Enables DAV on Port 1 SENSe EVENt PORTn DAVailable ENABle Returns the state of the DAVailable Event Enable for Port n as either a unsigned 0 or a 1 Parameters Comments A 0 means the DAVailable Event is disabled 1 means it is enabled RST Condition disables the interrupt Parameter Name Parameter Type Range ...

Page 54: ...NEDGE status registers for that port SENSe EVENt PORTn EDGE ENABle state Enables disables an edge event interrupt for Port n Parameters Comments Refer to the SENSe EVENt PORTn PEDGe ENAB or SENSe EVENt PORTn NEDGe ENAB commands to configure the edge detect registers The Edge Event Status is cleared by reading PEDGE and or NEDGE status registers for that port RST Condition not enabled Example EVEN ...

Page 55: ...a negative edge event was not detected for the corresponding bit of that port a 1 in any bit position indicates a negative edge event was detected for the corresponding bit of that port When an edge event is detected the Edge Detect Status is set true Refer to the SENSe EVENt PSUM EDGE and SENSe EVENt PORTn EDGE commands Reading this register for all events that have occurred will clear the event ...

Page 56: ...s of Port 1 SENSe EVENt PORTn NEDGe ENABle Returns the decimal value of the Negative Edge Detection Mask as a 16 bit integer Parameters Comments Returns a number in the range of 32768 to 32767 Each bit enables the corresponding channel negative edge detect mask for Port n A 1 means the mask is enabled for that bit a 0 means the mask is disabled for that bit RST Condition clears the mask no masked ...

Page 57: ...ading this register for all events that have occurred will clear the event detector register RST Condition disables the Edge Event SENSe EVENt PORTn PEDGe ENABle mask Sets the Positive Edge Detection Mask for Port n Parameters Comments Each bit enables the corresponding channel positive edge detect mask for Port n A 1 means the mask is enabled for that bit a 0 means the mask is disabled for that b...

Page 58: ...le Event for ALL ports as a 16 bit integer Parameters None Comments The value returned is in the range of 0 to 15 and is the sum of the following values This command is similar to the SENSe EVENt PORTn DAV command except that this command returns the status for all ports Example If the EVEN PSUM DAV command returns a value of 5 it indicates a DAV event occurred on Ports 0 and 2 values 1 and 4 resp...

Page 59: ...ar to the SENSe EVENt PORTn EDGe command except that this command returns the status for all ports Example If the EVEN PSUM EDGE command returns a value of 10 it indicates an edge event occurred on Ports 1 and 3 values 2 and 8 respectively see table Value Returned Meaning 0 No Edge Event occurred in any port 1 An Edge event occurred in Port 0 2 An Edge vent occurred in Port 1 4 An Edge vent occurr...

Page 60: ...uestionable Signal status register bit 3 and for the Standard Event registers is bit 5 Syntax STATus OPERation CONDition page 62 ENABle mask page 62 ENABle page 63 EVENt page 63 PSUMmary CONDition page 63 PSUMmary ENABle mask page 64 PSUMmary ENABle page 64 PSUMmary EVENt page 65 PRESet page 65 QUEStionable CONDition page 66 ENABle mask page 66 ENABle page 67 EVENt page 67 The STATus system contai...

Page 61: ...HP E1459A SCPI Command Reference 61 Figure 3 1 HP E1459A Status System Register Diagram ...

Page 62: ...tus Operation Conditions The STATus PRESet command does not affect the Status Operation Conditions STATus OPERation ENABle mask Sets the value of the OPERation Status Enable Register Parameters Comments mask determines which OPERation Status conditions are summed See Figure 3 1 The events detected in the Port Summary Status Register are reported in bit 9 of the Operation Status Register which in t...

Page 63: ...Event Register CLS clears the contents of the Status Operation Event Register STAT PRESet does not affect the contents of the Status Operation Event Register but does disable reporting the summary of this register in the Status Byte Register STB STATus OPERation PSUMmary CONDition Returns the value of the OPERation Status Port Summary Condition Register as a signed 16 bit integer Parameters None C...

Page 64: ...espectively bits 4 through 7 reflect edge events on Ports 0 through 3 respectively See Figure 3 1 RST and CLS do not affect the value of the enable mask STATus PRESet sets the value of the enable mask to 0 Example STAT OPER PSUM ENAB 0xFFFF Enables all bits of the Operation Status Port Summary Enable Register STATus OPERation PSUMmary ENABle Returns the value of the Operation Status Port Summary E...

Page 65: ... affect the contents of the Status Operation Event Port Summary register but does disable the reporting of the summary of this register in bit 9 of the Status Operation Register STATus PRESet Presets the Status system registers and conditions Parameters None Comments Resets the following registers and conditions Register Action Register Action Status Byte none OPER Status condition none Standard E...

Page 66: ...ot affect the contents of the Status Questionable Conditions The STAT PRESet command does not affect the Status Questionable Conditions STATus QUEStionable ENABle mask Sets the value of the QUEStionable Status Enable Register Note The Questionable Status Condition Event and Enable registers exist for SCPI compliance only No status bits are defined or reported in these registers Parameters None Com...

Page 67: ...6 bit integer and then clears the register to 0 Note The Questionable Status Condition Event and Enable registers exist for SCPI compliance only No status bits are defined or reported in these registers Parameters None Comments No bits are defined This is a destructive read so that all register bits are cleared after the read is executed RST does not affect the contents of the Status Questionable ...

Page 68: ...e command returns the following string 64 Channel Isolated Digital Input Interrupt Example SYSTem CDEScription 1 Requests the module description SYSTem CTYPe number Returns the module card type Parameters Comments number must be equal to 1 since only one HP E1459A module is allowed in a single instrument logical address The command returns the following string HEWLETT PACKARD E1459A Z2404B 0 revis...

Page 69: ...the command returns 0 No error CLS clears the error buffer RST does not affect the error buffer Refer to Appendix C for possible error messages Example SYST ERR Requests the error messages SYSTem VERSion Returns the SCPI version to which this module complies Parameters None Comments Returns a decimal value in the form YYY R where YYY is the year and R is the revision number within that year Since ...

Page 70: ... edge detect positive edge mask negative edge detect negative edge mask QUEStionable and OPERation PSUMmary Status Enable Registers QUEStionable and OPERation Status Event Register QUEStionable and OPERation PORT Status Event Register QUEStionable and OPERation PSUM Status Event Register RST Resets the module Resets the module to the settings shown in the Power On and Reset State table following t...

Page 71: ... disables an edge event interrupt for Port n Returns state of the Edge Event Enable for Port n as a signed integer Returns value of Negative Edge Detect Register for 16 bits of Port n Sets the Negative Edge Detection Mask for Port n Returns value of Negative Edge Detection Mask as a 16 bit integer Returns value of Positive Edge Detect Register for 16 bits of Port n Sets the Positive Edge Detection...

Page 72: ...72 HP E1459A SCPI Command Reference ...

Page 73: ...able Power Requirements Voltage 5Vdc Peak Module Current IPM A 0 19 Dynamic Module Current IDM A 0 10 Watts Slot 1 0 Minimum Pulse Width 100µs debounce time Operating Range Debounce Programmable from 16 µS to 1074 S 5 Volt Supply Output voltage 4 5 to 5 5 V DC Maximum output current 16 mA Typical Time to Read 16 bit Word 4 µS using register access Terminal Module Screw type removable maximum wire ...

Page 74: ...74 HP E1459A Specifications ...

Page 75: ...externally triggered and has data available Watchdog Timer Control Status Register The watchdog timer on the module is enabled and pet using this register Command Register There are two of these registers each controls two ports used to control triggering and enabling interrupts Channel Data Register There are four of these registers one for each port these registers contain the current channel da...

Page 76: ...s via VXI READ and VXI WRITE commands the logical address is used to determine which VXI module is being accessed Note Refer to the HP E1406 Command Module documentation for usage of the VXI READ and VXI WRITE commands and other related commands The following commands are sent to the HP E1406 Command Module via the HP IB The following example shows a portion of an HP BASIC program The controller c...

Page 77: ...egister Definitions The following registers can be accessed on the HP E1459A ID Register base 00h Device Type Register base 02h Status Control Register base 04h Edge Interrupt Status Register base 06h Data Available Status Register base 08h Watchdog Timer Control Status Register base 0Ah Command Register of Port 0 2 base 10h Channel Data Register of Port 0 2 base 12h Positive Edge Detect Register ...

Page 78: ...tions Reading this register returns the current state of the status bits for the module Status Control Register base 04h NOTE Bits 8 and 9 are returned in the IACK response in the same bit positions WRITE R Reset to power on state by writing a 1 in this bit Must be set back to 0 BS Bank Select When 0 Port 0 and Port 1 data are accessed in registers b 10h through b 2Eh When 1 Port 2 and Port 3 data...

Page 79: ...ontrols if IRQ will be asserted when data becomes available due to an external trigger on any of the ports A 1 enables the IRQ and a 0 disables it The interrupt will only occur if the following is true The command register for at least one of the ports must have the data ready enable bit set in order to generate an interrupt This can be verified by reading the Data Available Status Register to ass...

Page 80: ...y reading the interrupt register that caused the edge detection to occur Data Available Status Register The Data Available Status Register base 08h indicates if an external trigger has occurred for any of the 4 ports There are 4 bits used in this register one for each port A bit will be asserted when the DAV ENAB bit and the INT EXT bit are set 1 in the command register for a port and an external ...

Page 81: ...d If bit 4 is high 1 Port 2 will be accessed All control bits default to 0 as the reset state Bit 0 enables 1 and disables 0 an edge event to be reported in the Edge Interrupt Status Register If this bit is 1 then any edge event captured in either the positive or negative edge detect registers will appear in the Edge Interrupt Status Register An interrupt will only occur on the backplane IRQ if bi...

Page 82: ...l trigger mode When set to 0 the DAV0 2 line cannot cause an interrupt Caution A potential hazard exists if software were to improperly program the HP E1459A to post data capture IRQ s with the internally selected 1 0 MHz clock source In this situation a DAV interrupt would be posted each microsecond if software were able to service at that rate and would cause software to continuously vector to i...

Page 83: ...esponding bit in the Positive Mask Register Once the register is read the data is automatically cleared A transition is only seen if it is held long enough to pass through the debouncers If bit 4 of the Control Status Register is low 0 Port 0 data is accessed If bit 4 is high 1 Port 2 data will be accessed Positive Edge Detect Register Port 0 2 Channels 0 15 32 47 base 14h For Positive Negative Ed...

Page 84: ...d If bit 4 is high 1 Port 2 data will be accessed Positive Mask Register Port 0 2 Channels 0 15 32 47 base 18h Negative Mask Register Port 0 2 The Negative Mask Register for Port 0 2 base 1Ah can be read or written This register enables the Negative Edge Detect Register to capture high to low transitions on individual channels When a bit is set to 1 in this register it enables that channel to be c...

Page 85: ...nd Port 1 are accessed Port 0 and Port 1 use the same debounce clock With BS 0 any value programmed into or read from this register will be the same as the register at b 2Eh When BS 1 in the Status Control Register the debounce clock for Port 2 and Port 3 are accessed Port 2 and Port 3 use the same debounce clock With BS 1 any value programmed into or read from this register will be the same as th...

Page 86: ...s latched using EXT1 3 input DAV ENAB 1 allows the DAV1 3 line to cause an interrupt if enabled in the Status register The DAV line is asserted when data is latched This 15 000Fh 30 5 Hz 32 8 mS 131 148 mS 16 0010h 15 3 Hz 65 5 mS 262 294 mS 17 0011h 7 63 Hz 131 mS 524 59 mS 18 0012h 3 82 Hz 262 mS 1 05 1 16 S 19 0013h 1 91 Hz 524 mS 2 1 2 36 S 20 0014h 0 954 Hz 1 05 S 4 2 4 72 S 21 0015h 0 477 Hz...

Page 87: ... from internal to external Therefore any capture clock which occurs within the internal external clock selection interval will not post a marker to the control FPGA and will be lost Channel Data Register Port 1 3 The Channel Data Register for Port 1 3 base 22h is read only This register returns the current last data that has been clocked into the data capture circuitry If bit 4 of the Control Stat...

Page 88: ...Port 1 3 is identical to those of Port 0 2 Negative Edge Detect Register Port 1 3 Channels 16 31 48 63 base 26h Positive Mask Register Port 1 3 The Positive Mask Register for Port 1 3 base 28h can be read or written If bit 4 of the Control Status Register is low 0 Port 1 data is accessed If bit 4 is high 1 Port 3 data will be accessed The operation of the Positive Mask Register for Port 1 3 is ide...

Page 89: ...ister Port 0 and Port 1 Port 2 and Port 3 base 2Eh When BS 0 in the Status Control Register the debounce clock for Port 0 and Port 1 are accessed Port 0 and Port 1 use the same debounce clock With BS 0 any value programmed into or read from this register will be the same as the register at b 2Eh When BS 1 in the Status Status Register the debounce clock for Port 2 and Port 3 are accessed Port 2 an...

Page 90: ... Hz 4 1 mS 16 4 18 4 mS 13 000Dh 122 Hz 8 2 mS 32 8 36 9 mS 14 000Eh 61 Hz 16 4 mS 65 5 73 8 mS 15 000Fh 30 5 Hz 32 8 mS 131 148 mS 16 0010h 15 3 Hz 65 5 mS 262 294 mS 17 0011h 7 63 Hz 131 mS 524 590 mS 18 0012h 3 82 Hz 262 mS 1 05 1 18 S 19 0013h 1 91 Hz 524 mS 2 1 2 36 S 20 0014h 0 954 Hz 1 05 S 4 2 4 72 S 21 0015h 0 477 Hz 2 1 S 8 39 9 43 S 22 0016h 0 238 Hz 4 2 S 16 8 18 9 S 23 0017h 0 119 Hz ...

Page 91: ...rogram you must have the HP SICL library the HP VISA library an HP IB interface module installed in your PC and an HP E2406 Command Module include visa h include stdio h include stdlib h ViSession viRM E1459 int main unsigned short id_reg dt_reg ID Device Type Registers unsigned short stat_reg Status Register register ViStatus errStatus Status from each VISA call Open the default resource manager ...

Page 92: ...lose returned 0x x n errStatus return 0 return VI_SUCCESS Output and Edge Detection Examples The following three programming examples demonstrate edge detection DAV and mixed programming methods Edge Interrupt Example This example is coded in HP BASIC for a System 9000 Series 300 linked to a HP E1406 Command Module via HPIB The example enables all four channel ports to detect both positive and neg...

Page 93: ... bits for port 2 360 OUTPUT Vxi_address VXI WRITE 128 24 1 365 unmask all 16 neg bits for port 2 370 OUTPUT Vxi_address VXI WRITE 128 26 1 375 unmask all 16 pos bits for port 3 380 OUTPUT Vxi_address VXI WRITE 128 40 1 385 unmask all 16 neg bits for port 3 390 OUTPUT Vxi_address VXI WRITE 128 42 1 400 405 set debounce to 16 uS 250KHz for ports 2 3 410 OUTPUT Vxi_address VXI WRITE 128 46 2 420 430 ...

Page 94: ... VXI READ 128 6 get int status register 820 ENTER Vxi_address E 830 ENABLE INTR 7 2 840 Istat BINAND E 15 850 DISP Port 0 G0 Port 1 G1 Port 2 G2 Port 3 G3 Intr Istat 860 END LOOP 870 880 Service 890 DISABLE INTR 7 895 disable E1459A ints port 0 1 select 900 OUTPUT Vxi_address VXI WRITE 128 4 0 910 920 A SPOLL Vxi_address 930 OUTPUT Vxi_address STAT OPER EVEN 940 ENTER Vxi_address S_op 950 OUTPUT V...

Page 95: ...port 2 3 select 1360 OUTPUT Vxi_address VXI WRITE 128 4 16 1370 1375 get pos edge register port 2 1380 OUTPUT Vxi_address VXI READ 128 20 1390 ENTER Vxi_address A 1395 get neg edge register port 2 1400 OUTPUT Vxi_address VXI READ 128 22 1410 ENTER Vxi_address B 1420 PRINT Wrd 2 Pos Edge A 1430 PRINT Wrd 2 Neg Edge B 1440 1450 OUTPUT Vxi_address VXI READ 128 6 get int status register 1460 ENTER Vxi...

Page 96: ...7 120 OUTPUT Vxi_address RST CLS reset E1406 130 140 REPEAT 150 OUTPUT Vxi_address SYST ERR 160 ENTER Vxi_address Error 170 PRINT E1406 Reports Error Error 180 UNTIL Error 0 190 200 OUTPUT Vxi_address VXI WRITE 128 4 1 reset E1459A 210 WAIT 1 220 OUTPUT Vxi_address VXI WRITE 128 4 0 un reset E1459A 230 WAIT 1 240 245 dav enable ext clk port 0 250 OUTPUT Vxi_address VXI WRITE 128 16 6 255 mask off ...

Page 97: ...R ENAB 256 490 OUTPUT Vxi_address DIAG INT SET1 ON 500 OUTPUT Vxi_address DIAG INT ACT ON 510 520 OUTPUT Vxi_address OPC 530 ENTER Vxi_address Done 540 550 ON INTR 7 GOSUB Service 560 ENABLE INTR 7 2 565 dav int enable port 0 1 select 570 OUTPUT Vxi_address VXI WRITE 128 4 64 580 590 LOOP 600 DISABLE INTR 7 610 OUTPUT Vxi_address VXI READ 128 8 get dav status register 620 ENTER Vxi_address E 630 E...

Page 98: ... ENTER Vxi_address USING K E 1120 Istat BINAND E 15 1130 PRINT DAV Status Reg Istat 1140 PRINT 1150 1160 OUTPUT Vxi_address DIAG INT SET1 ON 1170 OUTPUT Vxi_address DIAG INT ACT ON 1180 OUTPUT Vxi_address OPC 1190 ENTER Vxi_address Done 1200 1210 ENABLE INTR 7 2 1215 dav int enabled port 0 1 select 1220 OUTPUT Vxi_address VXI WRITE 128 4 64 1230 1240 RETURN 1250 END Mixed Interupt Example This exa...

Page 99: ... high order 8 pos bits for port 1 330 OUTPUT Vxi_address VXI WRITE 128 36 256 335 unmask high order 8 neg bits for port 1 340 OUTPUT Vxi_address VXI WRITE 128 38 256 350 355 set debounce to 16 uS 250 KHz for ports 0 1 360 OUTPUT Vxi_address VXI WRITE 128 30 2 370 375 E1459A ints disabled port 2 3 select 380 OUTPUT Vxi_address VXI WRITE 128 4 16 390 395 dav enable ext clk edge enable port 2 400 OUT...

Page 100: ...INAND E 15 710 DISP DAV Status Reg Dstat EInt Status Reg Istat 720 END LOOP 730 740 Service 750 DISABLE INTR 7 755 disable E1459A ints port 0 1 select 760 OUTPUT Vxi_address VXI WRITE 128 4 0 770 780 A SPOLL Vxi_address 790 OUTPUT Vxi_address STAT OPER EVEN 800 ENTER Vxi_address S_op 810 OUTPUT Vxi_address DIAG INT RESP 820 ENTER Vxi_address R 830 840 REPEAT 850 OUTPUT Vxi_address SYST ERR 860 ENT...

Page 101: ...a Reg Port 2 A 1210 1215 get pos edge register port 2 1220 OUTPUT Vxi_address VXI READ 128 20 1230 ENTER Vxi_address C0 1235 get neg edge register port 2 1240 OUTPUT Vxi_address VXI READ 128 22 1250 ENTER Vxi_address C1 1260 1265 get dav data register port 3 1270 OUTPUT Vxi_address VXI READ 128 34 1280 ENTER Vxi_address A 1290 PRINT DAV Data Reg Port 3 A 1300 1305 get pos edge register port 3 1310...

Page 102: ...0 C BINAND C0 256 1680 PRINT Wrd 2 Pos Edge C 1690 C BINAND C1 256 1700 PRINT Wrd 2 Neg Edge C 1710 1715 get edge int status register 1720 OUTPUT Vxi_address VXI READ 128 6 1730 ENTER Vxi_address A 1740 A BINAND A 15 1750 PRINT EInt Status A 1760 1765 print wrd 3 edge registers 1770 D BINAND D0 256 1780 PRINT Wrd 3 Pos Edge D 1790 D BINAND D1 256 1800 PRINT Wrd 3 Neg Edge D 1810 1815 get edge int ...

Page 103: ...HP E1459A Register Definitions 103 1970 END ...

Page 104: ...104 HP E1459A Register Definitions ...

Page 105: ...t is enabled and an attempt is made to set the clock source to INTernal 222 Data out of range Data for a parameter is outside of limits For example an attempt to set debounce time to 10000 seconds 230 Data corrupt or stale Data available DAV is FALSE New data has not been clocked into the input circuitry since the input circuitry has been reprogrammed or since the last current value was read 2025 ...

Page 106: ...106 Error Messages ...

Page 107: ...guration 19 Connecting Inputs 22 D Data Capture 17 Debounce input processing 14 parameters 14 Description of module 11 DIAGnostic SYSReset ENABle 41 ENABle 42 STATe 41 Digital Input Mode 32 DISPlay MONitor PORT 43 AUTO 44 AUTO 44 PORT 44 STATe 45 STATe 45 E Edge Detection input 15 Edge interrupt resolver 13 Example Program Digital Input 32 Edge Interrupt 37 Reset 30 F Field Wiring 25 Front Panel M...

Page 108: ...cal Address 20 M Mainframe Installation 24 Markers front panel 18 MEASure DIGital DATAn type BITm 32 50 VALue 32 49 MEMory DELete MACRo 51 Module description 11 Module ID 30 P Parameters command 40 Polled Mode 18 Power on State 30 R Reset State 30 Resolver 13 S SCPI 29 39 Self Test 30 SENSe EVENt PORTn DAVailable ENABle 53 ENABle 53 DAVailable 52 EDGE ENABle 54 ENABle 55 EDGE 54 NEDGe ENABle 56 EN...

Page 109: ...Dition 66 ENABle 66 ENABle 67 EVENt 67 SYSTem CDEScription 68 CTYPe 68 ERRor 69 VERSion 69 T Terminal Block 25 Thresholds input 21 Timer Watchdog 14 21 U User Wiring 25 V VISA HP 29 Voltage input 11 W Watchdog Timer 14 21 Wiring 25 Wiring input 22 ...

Page 110: ...110 Index ...

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