The IRQ state machine monitors the following interrupt-related lines to
determine its actions: IACK*, valid DS0*, IACKIN*, AS*, ACKADDR*.
If the module is asserting IRQ and the interrupt-related lines are in the
proper state, the IRQ state machine asserts IRQX high (true) on U6.
IRQX high (true), inverted by USA, pulls the jumper-selected IRQ1* line
low (true) on the backplane. The state machine then waits for the interrupt
handler to recognize the interrupt request. When the interrupt handler
responds, it places the code for the interrupt request priority level that it is
acknowledging onto lines A1-A3. It then sets IACK* low (true) which sets
IACKIN* low (true).
IACK* low (true) starts the interrupt acknowledge cycle, disabling normal
address decoding on the breadboard module. When IACKIN* goes low
(true), the IRQ state machine checks to see if its own IRQ level has been
acknowledged (input line ACKADDR at U1 will be set low by a correct
match of U7’s decoded output and the jumper selection for IRQ
ACKNOWLEDGE).
If its own level is not being acknowledged, or if the module is not asserting
IRQ, the state machine passes the daisy-chained IACKIN* signal through
IACKOUT on U6. The IACKOUT signal is gated with an inverted AS* to
meet release time requirements for IACKOUT* as outlined in the VMEbus
Specification.
If the acknowledge level matches the request level, the IRQ state machine
sets PIACK* low (true), releases IRQX (and IRQ1*) and starts the DTACK
state machine for a read cycle. The interrupt handler initiates the read cycle
to get the logical device address from the interrupter when it sees IRQ1 * go
low (true). PIACK* low (true) enables U11 to place the module’s logical
address (from SP1) onto the lower eight bits of the internal data bus
(DB0-DB7).
The logical address is then transferred to backplane lines D0-D7 during the
read data transfer cycle. In this way, the interrupt handler knows which
device is asserting IRQ if more than one device has the same interrupt
priority assigned to it.
Chapter 2
Configuring the HP E1399A 33
Summary of Contents for E1399A
Page 6: ...Notes 6 HP E1399A Register Based Breadboard Module User s Manual ...
Page 8: ...8 HP E1399A Register Based Breadboard Module User s Manual ...
Page 11: ...Figure 1 1 Digital Backplane Interface Block Diagram Chapter 1 HP E1399A Introduction 11 ...
Page 14: ...14 HP E1399A Introduction Chapter 1 ...
Page 18: ...Figure 2 2 HP E1399A Dimensions 18 Configuring the HP E1399A Chapter 2 ...
Page 21: ...Figure 2 5 Terminal Module Installation Chapter 2 Configuring the HP E1399A 21 ...
Page 40: ...Figure 3 2 Timing for Reading the Status Register 40 Using the HP E1399A Chapter 3 ...
Page 43: ...Figure 3 4 Timing for Writing to the Control Register Chapter 3 Using the HP E1399A 43 ...
Page 45: ...Figure 3 5 Interrupt Timing Chapter 3 Using the HP E1399A 45 ...
Page 53: ...Appendix B HP E1399A Parts List Schematic 53 ...
Page 54: ...Figure B 1 HP E1399A Breadboard Schematic 1 of 2 54 HP E1399A Parts List Schematic Appendix B ...
Page 55: ...Figure B 1 HP E1399A Breadboard Schematic 2 of 2 Appendix B HP E1399A Parts List Schematic 55 ...
Page 56: ...56 HP E1399A Parts List Schematic Appendix B ...
