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HP E1399A, User Manual

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Terminal Module

An optional terminal module is available for making external connections to
the HP 1399A Breadboard Module. This module consists of a connector
mounted on a breadboard so that you can access the connector pins by
soldering wires to the breadboard. Figure 2-4 shows the layout of this
terminal module. Figure 2-5 shows how to make the connections and install
the module.

Warning

Since the inputs to the HP 1399A Breadboard Module are
through a 96-pin connector and a terminal card assembly, limit
voltage to 250Vdc/250Vrms.

For electrical shock protection, ensure that the module face
plate is securely tightened against the mainframe before
installing the terminal card.

Figure 2-4. Terminal Module Assembly

20  Configuring the HP E1399A

Chapter 2

Summary of Contents for E1399A

Page 1: ...ane Connections 16 Module Dimensions 16 Cooling Requirements 19 Terminal Module 20 Backplane Interface Circuitry 22 Address Lines and Register Decoding 22 Data Bus Drivers 25 Status Register 26 Device Type Register 27 Control Register 29 DTACK Interrupt and Control 30 User Access Points 35 Power Supplies 36 3 Using the HP E1399A 37 Reading Data From Registers 37 Status Register Bit Definitions 37 ...

Page 2: ...ting Errors 47 Using Other Power Supplies 48 A HP E1399A Breadboard Specifications 49 B HP E1399A Parts List Schematic 51 Terminal Block Parts List 51 Breadboard Parts List 52 Backplane Interface Schematic 52 Notes 2 HP E1399A Breadboard Module User s Manual Contents ...

Page 3: ...on this product is the sole responsibility of the Buyer HP does not warrant the Buyer s circuitry or malfunctions of HP products that result from the Buyer s circuitry In addition HP does not warrant any damage that oc curs as a result of the Buyer s circuit or any defects that result from Buyer supplied products NO OTHER WARRANTY IS EXPRESSED OR IMPLIED HP SPECIFICALLY DISCLAIMS THE IMPLIED WARRA...

Page 4: ...involving the removal of covers or shields are for use by service trained personnel only Under certain conditions dangerous voltages may exist even with the equipment switched off To avoid dangerous electrical shock DO NOT perform procedures involving cover or shield removal unless you are qualified to do so DO NOT operate damaged equipment Whenever it is possible that the safety protection featur...

Page 5: ...1991 Group1 Class A IEC 801 2 1991 EN50082 1 1992 4kVCD 8kVAD IEC 801 3 1984 EN50082 1 1992 3 V m IEC 801 4 1988 EN50082 1 1992 1kV Power Line 5kV Signal Lines Supplementary Information The product herewith complies with the requirements of the Low Voltage Directive 73 23 EEC and the EMC Directive 89 336 EEC and carries the CE marking accordingly Tested in a typical configuration in an HP B Size V...

Page 6: ...Notes 6 HP E1399A Register Based Breadboard Module User s Manual ...

Page 7: ... well organized O O O O O Instructions are easy to understand O O O O O The documentation is clearly written O O O O O Examples are clear and useful O O O O O Illustrations are clear and helpful O O O O O The documentation meets my overall expectations O O O O O Please write any comments or suggestions below be specific cut along this line fold here Your Name Company Name Job Title Address City St...

Page 8: ...8 HP E1399A Register Based Breadboard Module User s Manual ...

Page 9: ...ides HP part numbers and descriptions of all parts required by the HP E1399A It also includes a complete schematic of the E1399A digital backplane interface Specification Compliance Warranty The HP E1399A Breadboard Module is designed in full compliance with the VMEbus Specification Revision C 1 and the VXIbus specification Revision 1 3 The HP E1399A warranty statement located at the front of this...

Page 10: ...hows a block diagram of this interface Note For hardware operation a mnemonic suffixed with an asterisk such as WRITE indicates inverse logic 0 or low true 1 or high false A high state 1 is defined as a positive voltage usually 5 V and a low state 0 is defined as zero V ground at the specified signal point The HP E1399A interface features are Address Lines and Register Decoding The module implemen...

Page 11: ...Figure 1 1 Digital Backplane Interface Block Diagram Chapter 1 HP E1399A Introduction 11 ...

Page 12: ...t is possible to read the contents of the Status ID or Device Type Registers onto the data bus D0 D15 or to write information into the Control Register from the data bus DTACK The interface contains the circuitry required for generating a delayed DTACK data transfer acknowledge signal Interrupt Interface The breadboard module has D16 interrupter capability It does not contain an interrupt handler ...

Page 13: ...is available on the module to install your own custom circuitry This area does not include the portion of the circuit board required by the backplane interface components Component Height Lead Length The maximum component height allowed above the circuit board is 12 7 mm 0 5 in The maximum component lead length allowed below the circuit board is 1 3mm 0 05 in Warning Since the inputs to the HP1399...

Page 14: ...14 HP E1399A Introduction Chapter 1 ...

Page 15: ...power to the mainframe and to all external devices connected to the mainframe or to any of the modules For electrical shock protection ensure that the module face plate is securely tightened against the mainframe Warning Since the inputs to the HP 1399A Breadboard Module are through a 96 pin connector and a terminal card assembly limit voltage to 250Vdc 250Vrms Caution STATIC SENSITIVITY The backp...

Page 16: ...dule move your free hand to a metal surface on the mainframe thus bringing you the module and the mainframe to the same static potential Hardware Description Figure 2 1 shows the module with interface circuit components installed As shown the module consists of a circuit board with one backplane connector P1 and a front panel connector J1 Approximately one third of the circuit board contains trace...

Page 17: ...Figure 2 1 HP E1399A Breadboard Module Connector Pinout Chapter 2 Configuring the HP E1399A 17 ...

Page 18: ...Figure 2 2 HP E1399A Dimensions 18 Configuring the HP E1399A Chapter 2 ...

Page 19: ...d module it is not possible to specify cooling requirements without knowing the application and the amount of power to be dissipated Given the application however cooling requirements may be estimated as follows 1 Determine the airflow required as a function of power dissipation To maintain a 10ºC rise approximately 0 08 liters second are required for every watt dissipated For example if a module ...

Page 20: ...ws the layout of this terminal module Figure 2 5 shows how to make the connections and install the module Warning Since the inputs to the HP 1399A Breadboard Module are through a 96 pin connector and a terminal card assembly limit voltage to 250Vdc 250Vrms For electrical shock protection ensure that the module face plate is securely tightened against the mainframe before installing the terminal ca...

Page 21: ...Figure 2 5 Terminal Module Installation Chapter 2 Configuring the HP E1399A 21 ...

Page 22: ...e applicable and a parts list showing the components required by that group See Appendix B HP E1399A Parts List Schematic for a complete parts list and for a schematic of the entire backplane interface Note In the discussions of hardware operation that follow a high state 1 is indicated by a positive voltage usually 5 V and a low state 0 is indicated by zero V ground at the specified signal point ...

Page 23: ... 3975 1820 4242 1820 3631 1820 3079 1820 4147 Resistor Network 9 by 4 7kOhms Switch DIP 8 rocker 0 05A 30VDC IC 74HC541 Octal Line Driver IC 74HCT14 Schmitt Trigger Inverter IC 74HCT688N 8 bit Magnitude Comparator IC 74HC138N 3 to 8 Line Decoder IC 74HCT573 Octal D Type Latch Figure 2 6 Address Lines and Register Decoding Chapter 2 Configuring the HP E1399A 23 ...

Page 24: ...utput goes low This triggers a data transfer cycle using the DTACK state machine in the Interface IC U6 by the low at U6 input CADDR See DTACK Interrupt and Control for more information on the DTACK state machine As part of the data transfer cycle U6 sets DBEN low true latching the remaining backplane address lines A1 A5 at the U15 outputs to the two 3 to 8 line decoders U7 and U8 Latch U15 ensure...

Page 25: ...6 and U35 are enabled during a data bus transfer cycle when DBEN Data Bus Enable goes low true This occurs whenever the breadboard is correctly addressed by a match of the module s logical address as set by SP1 0 7 The direction of data transfer is determined by WRITE When WRITE is low a write operation information present on backplane lines D0 D15 is transferred to the breadboard Control Register...

Page 26: ...r Refer to the VXIbus Specification Section C 2 1 1 2 for detailed information concerning status register implementation restrictions Table 2 4 Status Register Bit Definitions Data Bit s Definitions SR0 SR1 SR2 SR3 SR4 SR7 Device Dependent User assignable 0 Failed Executing Self test 1 Passed Self test If 0 and Passed bit 1 Extended Self test active Device Dependent User assignable As shown in Fig...

Page 27: ...4 1810 0279 1820 3975 Resistor Network 9 by 4 7kOhm IC 74HC541 Octal Line Driver Device Type Register The Device Type Register is an 8 bit register which contains a device dependent module type identifier This field is set on the module by the use of an 8 position DIP switch on the inputs to the data bus line driver U10 as shown in Figure 2 9 Table 2 7 shows the resistor and IC part numbers for a ...

Page 28: ...e of device types for an A24 or A32 device is 0 4095 For an A16 device all 16 bits are available for specifying the device type for a range of 0 65535 The user will need to add the required buffer and resistor network to implement the full A16 device type range The default factory setting is FFxxh Note Per the VXIbus Specification OBSERVATION C 2 6 device types 0 255 are reserved for register base...

Page 29: ... 2 9 Control Register Parts Reference Designator HP Part Number Description U13 1820 4086 IC 74H T 73 Octal D Type Flip Flop Table 2 8 shows the Control Register bit definitions The Control Register is selected for writing to by the BASE 4 enable line see Table 2 2 BASE 4 going low at the input of U21C combined with a negative pulse for one clock cycle of SYSCLK from the LATCH output of U6 also ap...

Page 30: ...ontrol signals for standard data transfer cycles and interrupt requests acknowledgments Hardware and software reset signals together with a card fail signal have also been implemented DTACK The Data Transfer ACKnowledge DTACK circuitry is centered around the Interface IC U6 A state machine in this IC controls all read and write data transfer cycles Operation begins with the state machine in the id...

Page 31: ...kplane through U5C acknowledging to the system controller that the module has received the request for data and has placed the contents of the specified register onto the data lines With U16 and U35 enabled internal data lines DB0 DB15 are connected directly to the backplane data lines D0 D15 If the data transfer cycle is a write operation as indicated by WRITE low an additional state sets the U1 ...

Page 32: ...NOR Gate IC Interface PAL 74F38N Quad 2 input NAND Buffer IC 74HCT14 Hex Schmitt Trig Invrtr The VMEbus interrupt request levels IRQ1 IRQ7 are jumper selectable only one at a time allowed for both the IRQ request output line IRQ1 IRQ7 and the IRQ acknowledge input line ACKADDR IRQ request and acknowledge levels must always be the same IRQ1 is shown selected in Figure 2 12 To generate an interrupt ...

Page 33: ...ow by a correct match of U7 s decoded output and the jumper selection for IRQ ACKNOWLEDGE If its own level is not being acknowledged or if the module is not asserting IRQ the state machine passes the daisy chained IACKIN signal through IACKOUT on U6 The IACKOUT signal is gated with an inverted AS to meet release time requirements for IACKOUT as outlined in the VMEbus Specification If the acknowled...

Page 34: ...SYSFAIL INHBT line output of the Control Register CR1 is also low not inhibited then SYSFAIL is asserted System reset signal normally used to initialize the backplane interface circuitry and your own custom circuits to a known state Provides a hardware reset capability As implemented HRESET it clears the Status Register and the Control Register It also asserts the software reset line access point ...

Page 35: ...DS0 DS1 SR0 SR1 SR2 SR3 SR4 SR7 DBEN CRESET DTACK DTACK INH AS SYSFAIL SYSFAIL INH HRESET IRQ LATCH PIACK CADDR Backplane address lines A1 A5 latched ID Register Enable line Device Type Register Enable line Status and Control Registers Enable line User assignable Enable line User assignable Enable line User assignable Enable line User assignable Enable line User assignable Enable line Control Regi...

Page 36: ...er supplies they access to protect their mainframe All ground pins are connected together and are accessible in several places No ground loops are present in the module The front panel of the module is not grounded Table 2 15 Power Supply Voltages and Pin Numbers Voltage Connector and Pin Numbers 5 V dc 5V stdby 12 V dc 12 V dc P1 A32 B32 C32 P1 B31 P1 C31 P1 A31 36 Configuring the HP E1399A Chapt...

Page 37: ...itions It will be used as an example of how to read from a register on the breadboard module As shown in Table 3 1 only four of the eight bits in the register are predefined by the VXIbus Specification The other four bits are device dependent That is they can represent any condition that you define The inputs to the status register are provided by the user from the custom circuitry on the module A...

Page 38: ...ns SR0 SR1 SR2 SR3 SR4 SR7 Device Dependent User assignable 0 Failed Executing Self Test 1 Passed Self Test If 0 ands Passed bit 1 Extended Self Test Active Device Dependent User Assignable Figure 3 1 Status Register Access Points 38 Using the HP E1399A Chapter 3 ...

Page 39: ...ver U7 See Table 2 2 in Chapter 2 Must both be low 0 to enable 3 to 8 line decoder U8 Must equal the logical address of the module as set on DIP switch SP1 Must always be set high 1 to access the upper 16K of address space Must be set to either hexadecimal 29 101001 or hexadecimal 2D 10 1101 Refer to the VMEbus Specification and the VXIbus Specification Rule C 2 10 Must always be set high false si...

Page 40: ...Figure 3 2 Timing for Reading the Status Register 40 Using the HP E1399A Chapter 3 ...

Page 41: ...initions preassigned to control register data bits per the VXIbus Specification Section C 2 1 1 2 Table 3 3 Control Register Bit Definitions Data Bit s Definitions CR0 CR1 CR2 CR14 CR15 CRESET 1 Reset the module User defines reset actions SYSFAIL inhibit 1 Inhibit setting of SYSFAIL Reset 0 Safe Device Dependent User assignable 1 Enable access to A24 A32 Registers 0 Disable You may connect any of ...

Page 42: ...Must always be set high 1 to access the upper 16K of address space Must be set to either hexadecimal 29 10 1001 or hexadecimal 2D 10 1101 Refer to the VMEbus Specification and the VXIbus Specification Rule C 2 10 Must always be set high false since this is a 16D device short word transfer 16 bits or less 2 This is a write operation so WRITE must go low true to provide the LATCH signal from the DTA...

Page 43: ...Figure 3 4 Timing for Writing to the Control Register Chapter 3 Using the HP E1399A 43 ...

Page 44: ...request and accept the interrupt acknowledgment from the interrupt handler you must implement the following actions 1 You must provide the interrupt request from your custom circuits by setting the IRQ access point high 1 when the interrupt is to occur 2 Monitor PIACK after setting IRQ After PIACK goes low true and before it goes high false release IRQ or another interrupt will be generated 3 If y...

Page 45: ...Figure 3 5 Interrupt Timing Chapter 3 Using the HP E1399A 45 ...

Page 46: ...Figure 3 6 Interrupt Timing Wrong IRQ Level or No Interrupts Pending 46 Using the HP E1399A Chapter 3 ...

Page 47: ...se CRESET any way you choose in your custom circuitry Detecting Errors The breadboard module implements the following error fail circuitry The status register implements bit SR2 as a self test Passed Failed bit see Table 2 4 If SR2 PASSED access point is set low 0 indicating your custom circuit self test either failed or is currently still executing and the SYSFAIL INHBT bit CR1 output of the cont...

Page 48: ...ed by the power requirements of your customs circuitry See Cooling Requirements in Chapter 2 for more information on establishing cooling specifications for your module Recommended power supply voltage applications are listed in Table 3 5 Table 3 5 Power Supply Voltage Applications Supply Application 5 VDC 12 VDC 12 VDC 5 VDC Stdby Main power source for all systems Used for supplying power to logi...

Page 49: ...elow board VXIbus Interface Device Type Register Based VXIbus Interface Capability Slave Interrupter A16 D16 Interrupt Level 1 7 selectable Power and Cooling Maximum Power Dissipation Determined by mainframe cooling Cannot exceed the number of watts per module per slot total cooling backplane interface circuitry consumes 0 5 watts Power Requirements Voltage 5 Vdc Peak Module Current IPM A 0 10 Dyn...

Page 50: ...ipated At a power dissipation of 20W the pressure drop across a typically populated breadboard will be 0 05 mm H2O Environment Humidity 65 0 40 ºC Operating Temperature 0 55 ºC Storage Temperature 40 ºC to 70 ºC Safety EMI RFI Safety Me ets FTZ 1046 1984 CSA 556B IEC 348 UL 1244 50 HP E1399A Breadboard Specifications Appendix A ...

Page 51: ...e check digit abbreviated CD and the description Address the order to the nearest Hewlett Packard Sales and Support Office addresses are provided at the back of this manual Terminal Block Parts List HP Part Number Total Qty Description E1300 84401 E1300 01202 E1300 44101 1515 2109 1390 0846 E1399 66510 E1399 26510 0361 1294 1252 1593 1 1 1 1 2 1 1 2 1 Terminal Board Case Assembly Strain Relief Cla...

Page 52: ... 0099 by 0406LG Rivet 0099 by 0328LG Connector Right Angle 96 Pin IC Interface PAL Fixed Capacitor 15 µF 10 20 V Fixed Capacitor 0 1 µF 10 50 V Fixed Capacitor 0 1 µF 10 50V Fuse Subminiature 1A 125V Fixed Resistor 562 Ohm 1 1 8 W Resistor Network 9 by 4 7 kOhm 10 pin Resistor Network 9 by 4 7 kOhm 10 pin Switch DIP 8 rocker 0 05 A 30 V dc IC 74HCT02N Quad 2 input NOR Gate CMOS IC 74HC541N Octal L...

Page 53: ...Appendix B HP E1399A Parts List Schematic 53 ...

Page 54: ...Figure B 1 HP E1399A Breadboard Schematic 1 of 2 54 HP E1399A Parts List Schematic Appendix B ...

Page 55: ...Figure B 1 HP E1399A Breadboard Schematic 2 of 2 Appendix B HP E1399A Parts List Schematic 55 ...

Page 56: ...56 HP E1399A Parts List Schematic Appendix B ...

Page 57: ...on 5 Connectors 13 Control Register 12 29 41 Control Signals 34 Cooling Requirements 19 D Data Bus Drivers 25 Data Lines 10 Declaration of conformity 5 Description 10 16 Detecting Errors 47 Device Type Register 12 25 27 Dimensions 16 Documentation history 4 DTACK 12 30 E Errors 47 F Features 10 G Generating Interrupts 44 H Hardware 13 I ID Register 12 Interrupt Interface 12 Interrupts 30 44 L Logi...

Page 58: ...r 41 Device Type 27 Reading 37 Status 26 37 Writing 41 Reset 12 47 S Safety warnings 4 Schematic 52 Specifications 49 50 Status Register 12 25 26 37 Reading 39 T Terminal Block Parts List 51 Terminal Module 20 U User Access 35 W WARNINGS 4 Warranty 3 Writing to Control Register 41 Writing to Registers 41 58 HP E1399A Breadboard Module User s Manual Index ...

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