7-3
Product Design Considerations
Application Information
Bus Arbitration Considerations
The sections that follow discuss VME cycle time restrictions, FAIR arbitration restrictions,
and bus grant daisy chain.
Bus Grant Daisy Chain Each of the VME’s internal VME bus masters, processor to VME data
transfer controller, DMA controller, and the interrupt controller, function as separate devices in the bus
grant daisy chain. As a result, each request from an individual VME bus master of the Model 743/744
results in a unique assertion of BBSY and a unique VME bus request/grant on the bus arbitration daisy
chain.
System Integration
The System Integration section provides information for system integrators who are incorpo-
rating the HP 9000 Series Model 742i into the HP 9000 Series Model 748iVME systems and
the HP 9000 Series Model 743i or 744 into the HP 9000 Series Model 747i VME systems
running HP-UX into VME systems. Topics include hardware power-on information and
VME ASIC VME sysreset behavior.
Hardware Power On Information
The section that follows contains information about the Models 742i and 747i and the Mod-
els 743i, 744, and 748i at the time of power on.
VME ASIC Slave Behavior at Power On
The VME ASIC on the Model 742i responds to VME cycles immediately upon power on.
That is, VME cycles to A32 space in the address range 0x00000000 to 0x0fffffff are
acknowledged by the VME ASIC, running cycles into the onboard processor RAM. This
range of addresses is the default (power-on) location of the ASIC’s A32 direct map window.
The A32 VME address range of 0x00000000 to 0x00100000 is also acknowledged by the
ASIC’s A32 slave mapper, running cycles into onboard processor RAM (PA) physical
addresses of 0x0 to 0xfff). This power-on behavior cannot be disabled.
VME cycles to A24 space in the VME address range of 0x000000 to 0xfffff are acknowl-
edged by the VME ASIC, running cycles into onboard (PA) processor RAM. This range of
addresses is the default (power-on) location of the VME ASIC’s A24 direct map window and
of the A24 slave map window. This power-on behavior cannot be disabled.
VME cycles to A16, A24, and A32 space of the VME address range of 0x0000 to 0xfff are
acknowledged by the VME ASIC. This range of addresses is the default (power on) location
of the VME ASIC’s location monitor and FIFO register. This power on behavior cannot be
disabled.
When the HP-UX operating system is loaded, the VME A32 and A24 space mapped to
onboard processor RAM may be moved to another 256 MB boundary location in VME
space, based on the information that the EEPROM contains (the value of the EEPROM is set
through the vme_config program). The FIFO and location monitor may also be moved; how-
ever, the current HP-RT and HP-UX services do not use the FIFO and location monitor capa-
bilities.
The HP-RT operating system sets up the VME space for a conflict-free configuration based
on information provided during the system build process. However, if there is no local mem-
ory defined on an HP-RT processor, the Model 742’s default is still in place. This can lead to
a conflict if another memory area is assigned that overlaps the Model 742’s defaults.
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