57
-15 V On A2 Control Board. Voltage regulator A2U4 regulates the voltage across resistor A2R32 to be 1.25Vdc.
Circuit Included. -15 Vdc bias supply circuitry from connector pin A2P1-30 through test point A2J3-21 on A2 control
board.
Setup. The Main Troubleshooting Setup, Page 48. Apply the ac mains voltage to the bias transformer, and set the external
supply to 0Vdc.
Input:
NODE (+)
MEASUREMENT
SOURCE
A2U4(IN), A2C16 (-)
≈
- 24Vdc
A1U1, A1C1(+)
Outputs:
NODE ( + )
NODE (-)
MEASUREMENT
A2U4 (ADJ)
A2U24 (OUT)
l.25Vdc
A2VR2 (cath.)
A2VR2 (anode)
11.7Vdc
A2R33, A2R34
A2VR2 (cath.)
2.05Vdc
To check if load on -15V is shorted, remove jumper A2W3.
Refer to Down Programmer, for the + 8.9Vdc bias supply, and refer to OVP Circuit, for the + 2.5V bias supply.
Troubleshooting Down Programmer
The down programmer loads the output when either MASTER ENABLE is low or CV ERROR is more negative than about
- 6Vdc. Comparator A4U3B triggers down programming when the voltage at A4U3B-5 is less than about 3Vdc. The
collector-emitter current through transistor A4Q6 increases as the output voltage decreases because of feedback from
voltage divider A4R24-A4R27 at A4U3A-2
Circuit Included. Down programmer and 8.9V bias supply on A4 power mesh board.
Setup. The Main Troubleshooting Setup, Page 48, except connect the external supply to the unit’s + OUT ( + ) and - OUT
( - ) terminals. Apply the ac mains voltage to the bias transformer. Set the external supply (EXTERNAL) and adjust the
unit’s voltage setting (INTERNAL) as instructed below.
Outputs:
Set Voltage (Vdc)
NODE
External
Internal
Setup
Measurement
A4U4 (OUT)
-
-
8.9Vdc
A4U3B-7
0
2
unplug TS1
0Vdc
A4U3B-7
10
0
reconnect TS1
0Vdc
A4U3B-7
0
2
7.8Vdc
A4U3A-2
0
2
unplug TS1
0.43Vdc
A4R26
0
2
≈
0.41Vdc (6038A)
0.2Vdc (6033A)
A4Q6 (base)
20
2
1.0Vdc
A4U3A-1
20
2
4.0Vdc
A4R26
20
2
≈
0.34Vdc (6038A)
≈
0.11Vdc (6033A)
Summary of Contents for 6038A
Page 4: ......
Page 8: ......
Page 34: ...34 Figure 3 1 Troubleshooting Isolation ...
Page 35: ...35 Figure 3 1 Troubleshooting Isolation continued ...
Page 37: ...37 Figure 3 3 Clock and Primary SA Waveforms ...
Page 40: ...40 Figure 3 4 Readback and Secondary SA Waveforms ...
Page 56: ...56 Figure 3 7 Waveforms ...
Page 62: ...62 Figure 4 1 HP IB Block Diagram ...
Page 65: ...65 Figure 4 2 Front Panel Block Diagram ...
Page 90: ......
Page 93: ...93 Figure 6 1 Top View Top Covers Removed ...
Page 94: ...94 Figure 6 2 Main Board A1 Component Location ...
Page 95: ...95 Figure 6 3 Control Board A2 Component Location ...
Page 96: ...96 Figure 6 4 Front Panel Board A3 Component Location ...
Page 97: ...97 Figure 6 5 Power Mesh Board A4 Component Location ...
Page 98: ...98 Figure 6 6 HP IB Board A8 Component Location ...
Page 105: ...105 Figure 3 1 Troubleshooting Isolation option 001 ...
Page 106: ......