Holtek HT48R05A-1, Handbook, Page: 49 / 125

Under normal program operation, the WDT time-out will initialize a
²
chip reset
²
and set the status
bit
²
TO
²
. However, if the system is in the Power Down Mode, only a WDT time-out reset from
²
HALT
²
will be initialized which will only reset the Program Counter and Stack Pointer. Three meth-
ods can be adopted to clear the contents of the WDT including the WDT prescaler. The first is an
external hardware reset (a low level on the RES pin), the second is via software instructions and
the third is via a
²
HALT
²
instruction. There are two methods of using software instructions to clear
the Watchdog Timer, one of which must be chosen by configuration option. The first option is to
use the single
²
CLR WDT
²
instruction while the second is to use the two commands
²
CLR WDT1
²
and
²
CLR WDT2
²
. For the first option, a simple execution of
²
CLR WDT
²
will clear the WDT while
for the second option, both
²
CLR WDT1
²
and
²
CLR WDT2
²
must both be executed to successfully
clear the WDT. Note that for this second option, if
²
CLR WDT1
²
is used to clear the WDT, succes-
sive executions of this instruction will have no effect, only the execution of a
²
CLR WDT2
²
instruc-
tion will clear the WDT. Similarly, after the
²
CLR WDT2
²
instruction has been executed, only a
successive
²
CLR WDT1
²
instruction can clear the Watchdog Timer.
42
Cost-Effective I/O Type MCU
f
S Y S
/ 4
8 - b i t C o u n t e r
(
¸
2 5 6 )
7 - b i t P r e s c a l e r
8 - t o - 1 M U X
W D T T i m e - o u t
W S 0 ~ W S 2
C o n f i g .
O p t i o n
S e l e c t
W D T O S C O u t p u t
W D T S o u r c e S e l e c t
C o n t r o l
L o g i c
C L R W D T 1 F l a g
C L R W D T 2 F l a g
1 o r 2 I n s t r u c t i o n s
C L R
C L R
Watchdog Timer