Holtek HT48R05A-1, Handbook, Page: 18 / 125

System Architecture
A key factor in the high-performance features of the Holtek range of Cost-Effective I/O Type
microcontrollers is attributed to the internal system architecture. The range of devices take advan-
tage of the usual features found within RISC microcontrollers providing increased speed of opera-
tion and enhanced performance. The pipelining scheme is implemented in such a way that
instruction fetching and instruction execution are overlapped, hence instructions are effectively ex-
ecuted in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in
practically all operations of the instruction set. It carries out arithmetic operations, logic operations,
rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by mov-
ing data through the Accumulator and the ALU. Certain internal registers are implemented in the
Data Memory and can be directly or indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external com-
ponents is required to provide a functional I/O control system with maximum reliability and flexibil-
ity. This makes these devices suitable for low-cost, high-volume production for controller
applications requiring from 0.5K up to 2K words of program memory and from 32 to 96 bytes of
data storage.
Clocking and Pipelining
The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into
four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at
the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecu-
tive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the con-
tents of the Program Counter are changed, such as subroutine calls or jumps, in which case the in-
struction will take one more instruction cycle to execute.
Note When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This
T1 phase clock has a frequency of f
SYS
/4 with a 1:3 high/low duty cycle.
Chapter 1 Hardware Structure
11
F e t c h I n s t . ( P C )
E x e c u t e I n s t . ( P C - 1 )
F e t c h I n s t . ( P C + 1 )
E x e c u t e I n s t . ( P C )
F e t c h I n s t . ( P C + 2 )
E x e c u t e I n s t . ( P C + 1 )
P C P C + 1 P C + 2
O s c i l l a t o r C l o c k
( S y s t e m C l o c k )
P h a s e C l o c k T 1
P r o g r a m C o u n t e r
P h a s e C l o c k T 2
P h a s e C l o c k T 3
P h a s e C l o c k T 4
P i p e l i n i n g
System Clocking and Pipelining