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Rev. 1.00

46

August 29, 2018

Rev. 1.00

47

August 29, 2018

HT45F6530

AC Voltage Regulator Flash MCU

HT45F6530

AC Voltage Regulator Flash MCU

or when a stack level becomes free. The other situation is where the related interrupt is enabled and
the stack is not full, in which case the regular interrupt response takes place. If an interrupt request
flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related
interrupt will be disabled.

Watchdog Timer

The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.

Watchdog Timer Clock Source

The Watchdog Timer clock source is provided by the internal clock, f

LIRC

which is sourced from

the LIRC oscillator. The LIRC internal oscillator has an approximate frequency of 32kHz and this

specified internal clock period can vary with V

DD

, temperature and process variations. The Watchdog

Timer source clock is then subdivided by a ratio of 2

8

to 2

15

to give longer timeouts, the actual value

being chosen using the WS2~WS0 bits in the WDTC register.

Watchdog Timer Control Register

A single register, WDTC, controls the required time-out period as well as the enable/disable and
reset MCU operation.

• WDTC Register

Bit

7

6

5

4

3

2

1

0

Name

WE4

WE3

WE2

WE1

WE0

WS2

WS1

WS0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

1

0

1

0

0

1

1

Bit 7~3

WE4~WE0

: WDT function control

10101: Disable

01010: Enable

Other values: Reset MCU

When these bits are changed to any other values due to environmental noise the

microcontroller will be reset; this reset operation will be activated after a delay time,

t

SRESET

, and the WRF bit in the RSTFC register will be set high.

Bit 2~0

WS2~WS0

: WDT time-out period selection

000: 2

8

/f

LIRC

001: 2

9

/f

LIRC

010: 2

10

/f

LIRC

011: 2

11

/f

LIRC

100: 2

12

/f

LIRC

101: 2

13

/f

LIRC

110: 2

14

/f

LIRC

111: 2

15

/f

LIRC

These three bits determine the division ratio of the Watchdog Timer source clock,

which in turn determines the time-out period.

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Summary of Contents for HT45F6530

Page 1: ...AC Voltage Regulator Flash MCU HT45F6530 Revision V1 00 Date August 29 2018 ...

Page 2: ...acteristics 13 Input Output Characteristics 14 Memory Characteristics 14 LVR LVD Electrical Characteristics 15 Internal Reference Voltage Characteristics 15 A D Converter Electrical Characteristics 16 PGA Electrical Characteristics 16 Over Current Protection Electrical Characteristics 17 D A Converter Electrical Characteristics 17 Operational Amplifier Electrical Characteristics 17 Comparator Elec...

Page 3: ...ing Data to the EEPROM 35 Write Protection 35 EEPROM Interrupt 35 Programming Considerations 35 Oscillators 37 Oscillator Overview 37 System Clock Configurations 37 Internal High Speed RC Oscillator HIRC 38 Internal 32kHz Oscillator LIRC 38 Operating Modes and System Clocks 38 System Clocks 38 System Operation Modes 39 Control Register 40 Operating Mode Switching 42 Standby Current Considerations ...

Page 4: ...r Input Signals 76 A D Converter Operation 77 Conversion Rate and Timing Diagram 78 Summary of A D Conversion Steps 79 Programming Considerations 80 A D Conversion Function 80 A D Conversion Programming Examples 80 Over Current Protection OCP 82 Over Current Protection Operation 82 Over Current Protection Registers 83 Offset Calibration Procedure 87 Low Voltage Detector LVD 88 LVD Register 88 LVD ...

Page 5: ...truction Timing 102 Moving and Transferring Data 102 Arithmetic Operations 102 Logical and Rotate Operation 103 Branches and Control Transfer 103 Bit Operations 103 Table Read Operations 103 Other Operations 103 Instruction Set Summary 104 Table Conventions 104 Instruction Definition 106 Package Information 115 20 pin NSOP 150mil Outline Dimensions 116 24 pin SOP 300mil Outline Dimensions 117 24 p...

Page 6: ...ne or two instruction cycles Table read instructions 63 powerful instructions 4 level subroutine nesting Bit manipulation instruction Peripheral Features Flash Program Memory 2K 15 RAM Data Memory 128 8 True EEPROM Memory 32 8 Watchdog Timer function 22 bidirectional I O lines Two pin shared external interrupts Multiple Timer Modules for time measurement compare match output or PWM output function...

Page 7: ... Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments The device also includes fully integrated high and low speed oscillators which require no external components for their implementation The ability to operate and switch dynamically between a range of operating modes using different...

Page 8: ...CDSCK ICPCK PA0 CTP0 VR1EXT INT0 OCDSDA ICPDA HT45F6530 HT45V6530 20 NSOP A 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 PB5 CMP1N CTP1B PB7 CMP1O CTCK1 PB6 CMP1P PC0 CMP0O CTCK0 PC1 BUF_OUT0 PC2 OPA1P PC3 OPA1N PB0 BUF_OUT1 PC4 OPA0P PC5 OPA0N PA2 CTP1 VR0EXT OCDSCK ICPCK PA0 CTP0 VR1EXT INT0 OCDSDA ICPDA PA1 AN5 VREF PA3 AN4 VREFI PA4 AN3 INT1 PA5 AN2 PA6 AN1 PA7 AN0 VSS VDD PB1 OPA1O PB2 ...

Page 9: ...address for EV chip only ICPDA ST CMOS ICP data address PA1 AN5 VREF PA1 PAPU PAWU PAS0 ST CMOS General purpose I O Register enabled pull up and wake up AN5 PAS0 AN A D Converter external input channel VREF PAS0 AN A D Converter reference voltage input PA2 CTP1 VR0EXT OCDSCK ICPCK PA2 PAPU PAWU PAS0 ST CMOS General purpose I O Register enabled pull up and wake up CTP1 PAS0 CMOS CTM1 output VR0EXT ...

Page 10: ...ister enabled pull up CMP1N PBS1 AN Comparator 1 negative input CTP1B PBS1 CMOS CTM1 inverted output PB6 CMP1P PB6 PBPU PBS1 ST CMOS General purpose I O Register enabled pull up CMP1P PBS1 AN Comparator 1 positive input PB7 CMP1O CTCK1 PB7 PBPU PBS1 ST CMOS General purpose I O Register enabled pull up CMP1O PBS1 CMOS Comparator 1 output CTCK1 PBS1 ST CTM1 clock input PC0 CMP0O CTCK0 PC0 PCPU PCS0 ...

Page 11: ...liability D C Characteristics For data in the following tables note that factors such as oscillator type operating voltage operating frequency pin load conditions temperature and program instruction type etc can all exert an influence on the measured values Operating Voltage Characteristics Ta 40 C 85 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Operating Voltage HIRC fSYS fHIRC 8MHz 2 ...

Page 12: ... For data in the following tables note that factors such as oscillator type operating voltage operating frequency and temperature etc can all exert an influence on the measured values High Speed Internal Oscillator HIRC Frequency Accuracy During the program writing operation the writer will trim the HIRC oscillator at a user selected HIRC frequency and user selected voltage of either 3V or 5V Symb...

Page 13: ...RC tRSTD System Reset Delay Time Reset source from Power on reset or LVR hardware reset RRPOR 5V ms 25 50 150 ms System Reset Delay Time WDTC software reset System Reset Delay Time Reset source from WDT overflow 8 3 16 7 50 0 ms tSRESET Minimum Software Reset Width to Reset 45 90 375 μs Note 1 For the System Start up time values whether fSYS is on or off depends upon the mode type and the chosen f...

Page 14: ...se Width 0 3 μs tINT External Interrupt Minimum Pulse Width 10 μs Note The RPH internal pull high resistance value is calculated by connecting to ground and enabling the input pin with a pull high resistor and then measuring the pin current at the specified supply voltage level Dividing the voltage by this measured current provides the RPH value Memory Characteristics Ta 40 C 85 C unless otherwise...

Page 15: ...BGEN 1 25 5V 25 30 ILVR Additional Current for LVR Enable LVD disable VBGEN 0 24 μA ILVD Additional Current for LVD Enable LVR disable VBGEN 0 24 μA tLVDS LVDO Stable Time For LVR enable VBGEN 0 LVD off on 18 μs For LVR disable VBGEN 0 LVD off on 150 tLVR Minimum Low Voltage Width to Reset 140 600 1000 μs tLVD Minimum Low Voltage Width to Interrupt 40 150 320 μs Internal Reference Voltage Characte...

Page 16: ...B VREF VDD tADCK 10μs 5V IADC Additional Current for A D Converter Enable 3V No load tADCK 0 5μs 0 2 0 4 mA 5V 0 3 0 6 tADCK A D Clock Period 0 5 10 μs tON2ST A D Converter On to Start Time 4 μs tADS A D Sampling Time 4 tADCK tADC A D Conversion Time Include A D Sample and Hold Time 16 tADCK PGA Electrical Characteristics Ta 40 C 85 C unless otherwise specified Symbol Parameter Test Conditions Min...

Page 17: ...V Code 0FFFH 2 mA 5V 6 Operational Amplifier Electrical Characteristics Ta 40 C 85 C typical Ta 25 C unless otherwise specified Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VDD Operating Voltage 2 2 5 5 V IOPA Operating Current 5V OPnBW 1 0 00B no load 3 0 5 0 μA OPnBW 1 0 01B no load 10 16 OPnBW 1 0 10B no load 80 128 OPnBW 1 0 11B no load 200 320 VOS Input Offset Voltage 5V W...

Page 18: ...ditions Min Typ Max Unit VDD Conditions IOPA Operating Current OPnBW 1 0 00B no load 2 5 4 0 μA OPnBW 1 0 01B no load 10 16 OPnBW 1 0 10B no load 80 128 OPnBW 1 0 11B no load 200 320 VOS Input Offset Voltage Without calibration OnOF 5 0 100000B 15 15 mV With calibration 6 6 IOS Input Offset Current VIN 1 2VCM 1 10 nA VCM Common Mode Voltage Range OPnBW 1 0 00 01 10 11 VSS VDD 1 4 V PSRR Power Supp...

Page 19: ...cs Ta 25 C All measurement is under CMPnP input voltage VDD 1 4 2 and remain constant Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VDD Operating Voltage 2 7 5 5 V ICMP Additional Current for Comparator Enable 3V CNVTn 1 0 00B 3 μA 5V 1 3 3V CNVTn 1 0 01B 22 μA 5V 14 22 3V CNVTn 1 0 10B 57 μA 5V 36 57 3V CNVTn 1 0 11B 92 μA 5V 58 92 VOS Input Offset Voltage 3V Without calibratio...

Page 20: ...s 5V 1 5 4 3V With 10mV overdrive 2 CNVTn 1 0 10B 0 8 2 μs 5V 0 8 2 3V With 10mV overdrive 2 CNVTn 1 0 11B 0 7 1 5 μs 5V 0 7 1 5 Note 1 If VIN comparing threshold is lower than 250mV the offset voltage could be over 4mV It is recommended to recalibrate the offset voltage first when the comparing level is lower than 250mV 2 Load Condition CLOAD 50pF Load Condition CLOAD VSS Pin Power on Reset Chara...

Page 21: ...tions Clocking and Pipelining The main system clock derived from either a HIRC or LIRC oscillator is subdivided into four internally generated non overlapping clocks T1 T4 The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched The remaining T2 T4 clocks carry out the decoding and execution functions In this way one T1 T4 clock cycle forms...

Page 22: ...ort program jump can be executed directly however as only this low byte is available for manipulation the jumps are limited to the present page of memory that is 256 locations When such program jumps are executed it should also be noted that a dummy cycle will be inserted Manipulating the PCL register may cause program branching so an extra cycle is needed to pre fetch Stack This is a special part...

Page 23: ...DM ADC ADCM SUB SUBM SBC SBCM DAA Logic operations AND OR XOR ANDM ORM XORM CPL CPLA Rotation RRA RR RRCA RRC RLA RL RLCA RLC Increment and Decrement INCA INC DECA DEC Branch decision JMP SZ SZA SNZ SIZ SDZ SIZA SDZA CALL RET RETI Flash Program Memory The Program Memory is the location where the user code or program is stored For the device the Program Memory is Flash type which means it can be pr...

Page 24: ...e table pointer the table data can be retrieved from the Program Memory using the TABRDC m or TABRDL m instructions respectively When the instruction is executed the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register m as specified in the instruction The higher order table data byte from the Program Memory will be transferred to the TBLH spe...

Page 25: ...ons require two instruction cycles to complete their operation Table Read Program Example tempreg1 db temporary register 1 tempreg2 db temporary register 2 mov a 06h initialize table pointer note that this address is referenced mov tblp a to the last page or present page tabrdl tempreg1 transfers value in table referenced by table pointer to tempreg1 data at program memory address 0706H transferre...

Page 26: ...p Debug Support OCDS There is an EV chip named HT45V6530 which is used to emulate the real MCU device named HT45F6530 The EV chip device also provides the On Chip Debug function to debug the real MCU device during development process The EV chip and real MCU device HT45V6530 and HT45F6530 are almost functional compatible except the On Chip Debug function Users can use the EV chip device to emulate...

Page 27: ...Bank 1 Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value The start address of the Data Memory for the device is the address 00H The address range of the Special Purpose Data Memory for the device is from 00H to 7FH while the address range of the General Purpose Data Memory is from 80H to FFH Special Purpose Data Memory General Purpose Da...

Page 28: ...H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Bank 0 Bank 1 Bank 0 Bank 1 IAR0 MP0 IAR1 MP1 BP ACC PCL TBLP TBLH STATUS RSTFC HIRCC SCC PA PAC PAPU PAWU EEA WDTC Unused read as 00H 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH CTM1C0 CTM0C0 CTM0AH CTM0DL CTM0DH CTM0AL CTM0C1 PAS0 PAS1 EED SADOL SADC0 SADC1 SADC2 SADOH EEC 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4C...

Page 29: ...mory Pointers MP0 MP1 Two Memory Pointers known as MP0 and MP1 are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data When any operation to the relevant Indirect Addressing Registers is carried out the actual address that the microcontroller is direct...

Page 30: ...the temporary storage function of the Accumulator for example when transferring data between one user defined register and another it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted Program Counter Low Register PCL To provide additional program control functions the low byte of the Program Counter is made accessible to pr...

Page 31: ...latest operations C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation otherwise C is cleared C is also affected by a rotate through carry instruction AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction otherwise AC i...

Page 32: ...verflow 1 An operation results in a carry into the highest order bit but not a carry out of the highest order bit or vice versa Bit 2 Z Zero flag 0 The result of an arithmetic or logical operation is not zero 1 The result of an arithmetic or logical operation is zero Bit 1 AC Auxiliary flag 0 No auxiliary carry 1 An operation results in a carry out of the low nibbles in addition or no borrow from ...

Page 33: ...ss and a data register in Bank 0 and a single control register in Bank 1 EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory These are the address registers EEA the data register EED and a single control register EEC As both the EEA and EED registers are located in Bank 0 they can be directly accessed in the same way as any other Special Function Regis...

Page 34: ... is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle This bit will be automatically reset to zero by the hardware after the read cycle has finished Setting this bit high will have no effect if the RDEN has not first been set high Note 1 The WREN WR RDEN and RD cannot be set high at the same time in one instruction The WR and RD cannot be set ...

Page 35: ...ta Memory Bank 0 will be selected As the EEPROM control register is located in Bank 1 this adds a further measure of protection against spurious write operations During normal program operation ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle ha...

Page 36: ...OV A EED move read data to register MOV READ_DATA A Note For each read operation the address register should be re specified followed by setting the RD bit high to activate a read cycle even if the target address is consecutive Writing Data to the EEPROM polling method MOV A EEPROM_ADRES user defined address MOV EEA A MOV A EEPROM_DATA user defined data MOV EED A MOV A 040H setup memory pointer MP...

Page 37: ...y to optimise the performance power ratio a feature especially important in power sensitive portable applications Type Name Frequency Internal High Speed RC HIRC 8MHz Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are two methods of generating the system clock one high speed oscillator and one low speed oscillator The high speed oscillator is the internal 8MHz ...

Page 38: ...that their microcontrollers have high performance but often still demand that they consume as little power as possible conflicting requirements that are especially true in battery powered portable applications The fast clocks required for high performance will by their nature increase current consumption and of course vice versa lower speed clocks reduce current consumption As Holtek has provided ...

Page 39: ...ller each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application There are two modes allowing normal operation of the microcontroller the FAST Mode and SLOW Mode The remaining four modes the SLEEP IDLE0 IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve power Operation Mode...

Page 40: ...he fLIRC clock can still continue to operate if the WDT function is enabled the fLIRC clock will be stopped too if the Watchdog Timer function is disabled IDLE0 Mode The IDLE0 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is low and the FSIDEN bit in the SCC register is high In the IDLE0 Mode the CPU will be switched off but the low speed oscillat...

Page 41: ... Enable This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an HALT instruction Bit 0 FSIDEN Low frequency oscillator control when CPU is switched off 0 Disable 1 Enable This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an HALT instruction HIRCC R...

Page 42: ...IDEN bits in the SCC register FAST fSYS fH fH 64 fH on CPU run fSYS on fSUB on SLOW fSYS fSUB fSUB on CPU run fSYS on fH on off IDLE0 HALT instruction executed CPU stop FHIDEN 0 FSIDEN 1 fH off fSUB on IDLE1 HALT instruction executed CPU stop FHIDEN 1 FSIDEN 1 fH on fSUB on IDLE2 HALT instruction executed CPU stop FHIDEN 1 FSIDEN 0 fH on fSUB off SLEEP HALT instruction executed CPU stop FHIDEN 0 F...

Page 43: ...et to 000 110 and then the system clock will respectively be switched to fH fH 64 However if fH is not used in SLOW mode and thus switched off it will take some time to re oscillate and stabilise when switching to the FAST mode from the SLOW Mode This is monitored using the HIRCF bit in the HIRCC register The time duration required for the high speed system oscillator stabilization is specified in...

Page 44: ...ory contents and registers will maintain their present condition The I O ports will maintain their present conditions In the status register the Power Down flag PDF will be set and WDT timeout flag TO will be cleared The WDT will be cleared and resume counting if the WDT function is enabled If the WDT function is disabled the WDT will be cleared and stopped Entering the IDLE1 Mode There is only on...

Page 45: ...2 Mode the high speed oscillator is on if the peripheral function clock source is derived from the high speed oscillator the additional standby current will also be perhaps in the order of several hundred micro amps Wake up To minimise power consumption the device can enter the SLEEP or any IDLE Mode where the CPU will be switched off However when the device is woken up again it will take a consid...

Page 46: ...and process variations The Watchdog Timer source clock is then subdivided by a ratio of 28 to 215 to give longer timeouts the actual value being chosen using the WS2 WS0 bits in the WDTC register Watchdog Timer Control Register A single register WDTC controls the required time out period as well as the enable disable and reset MCU operation WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE...

Page 47: ...WE4 WE0 bits are set to a value of 10101B while the WDT function will be enabled if the WE4 WE0 bits are equal to 01010B If the WE4 WE0 bits are set to any other values other than 01010B and 10101B it will reset the device after a delay time tSRESET After power on these bits will have a value of 01010B WE4 WE0 Bits WDT Function 10101B Disable 01010B Enable Any other value Reset MCU Watchdog Timer ...

Page 48: ...ocontroller to begin program execution from the lowest Program Memory address In addition to the power on reset another reset exists in the form of a Low Voltage Reset LVR where a full reset is implemented in situations where the power supply voltage falls below a certain threshold Another type of reset is when the Watchdog Timer overflows and resets the microcontroller All types of reset operatio...

Page 49: ...ignore the low supply voltage and will not perform a reset function Note that the LVR function will be automatically disabled when the device enters the SLEEP or IDLE mode LVR Internal Reset tRSTD tSST Note tRSTD is power on delay typical time 50ms Low Voltage Reset Timing Chart RSTFC Register Bit 7 6 5 4 3 2 1 0 Name LVRF WRF R W R W R W POR x 0 x unknown Bit 7 3 Unimplemented read as 0 Bit 2 LVR...

Page 50: ...Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Time Bases Clear after reset WDT begins counting Timer Modules Timer Modules will be turned off Input Output Ports I O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways To ens...

Page 51: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTM0C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTM0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTM0DH 0 0 0 0 0 0 u u CTM0AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTM0AH 0 0 0 0 0 0 u u CTM1C0 0 0...

Page 52: ...0C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u CMP0VOS 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 u u u u u u u OP0C 0 0 0 0 0 0 0 0 0 0 0 0 u u u u OP0VOS 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 u u u u u u u u DA1H 0 0 0 0 0 0 0 0 0 0 0 0 u u u u DA1L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u DAC1C 0 0 0 0 0 0 0 0 0 0 0 0 u u u u CMP1C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u...

Page 53: ...AWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 Unimplemented read as 0 I O Logic Function Register List Pull high Resistors Many product applications require pull high resistors for th...

Page 54: ...control Each pin of the I O ports is directly mapped to a bit in its associated port control register For the I O pin to function as an input the corresponding bit of the control register must be written as a 1 This will then allow the logic state of the input pin to be directly read by instructions When the corresponding bit of the control register is written as a 0 the I O pin will be setup as a...

Page 55: ...e pin shared control configuration with their corresponding general purpose I O functions when setting the relevant pin shared control bit fields To select these pin functions in addition to the necessary pin shared control and peripheral functional setup aforementioned they must also be setup as an input by setting the corresponding bit in the I O port control register To correctly deselect the p...

Page 56: ...ed function selection 00 PA6 01 PA6 10 PA6 11 AN1 Bit 3 2 PAS13 PAS12 PA5 Pin Shared function selection 00 PA5 01 PA5 10 PA5 11 AN2 Bit 1 0 PAS11 PAS10 PA4 Pin Shared function selection 00 PA4 INT1 01 PA4 INT1 10 PA4 INT1 11 AN3 PBS0 Register Bit 7 6 5 4 3 2 1 0 Name PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PBS07 PBS06 PB3 Pin ...

Page 57: ...n Shared function selection 00 PB6 01 PB6 10 PB6 11 CMP1P Bit 3 2 PBS13 PBS12 PB5 Pin Shared function selection 00 PB5 01 CTP1B 10 PB5 11 CMP1N Bit 1 0 PBS11 PBS10 PB4 Pin Shared function selection 00 PB4 01 CTP0B 10 PB4 11 CMP0N PCS0 Register Bit 7 6 5 4 3 2 1 0 Name PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PCS07 PCS06 PC3 Pin...

Page 58: ...C4 11 OPA0P I O Pin Structures The accompanying diagram illustrates the internal structure of the I O logic function As the exact logical construction of the I O pin will differ from this drawing it is supplied as a guide only to assist with the functional understanding of the I O logic function The wide range of pin shared structures does not permit all types to be shown M U X VDD Control Bit Dat...

Page 59: ...e of the most fundamental functions in any microcontroller device is the ability to control and measure time To implement time related functions the device includes several Timer Modules abbreviated to the name TM The TMs are multi purpose timing units and serve to provide operations such as Timer Counter Compare Match Output as well as being the functional unit for the generation of PWM signals E...

Page 60: ... pin can be chosen to have either a rising or falling active edge The TMs each have two output pins with the label CTPn and CTPnB When the TM is in the Compare Match Output Mode these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs The external CTPn and CTPnB output pins are also the pins where the TM generates the PWM output wav...

Page 61: ...ad Write The following steps show the read and write procedures Writing Data to CCRA Step 1 Write data to Low Byte CTMnAL Note that here data is only written to the 8 bit buffer Step 2 Write data to High Byte CTMnAH Here data is written directly to the high byte registers and simultaneously data is latched from the 8 bit buffer to the Low Byte registers Reading Data from the Counter Registers and ...

Page 62: ...mparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP comparator is 3 bit wide whose value is compared with the highest 3 bits in the counter while the CCRA is the 10 bits and therefore compares all counter bits The only way of changing the value of the 10 bit counter using the application program is to clear the counter by changi...

Page 63: ... 000 fSYS 4 001 fSYS 010 fH 16 011 fH 64 100 fSUB 101 fSUB 110 CTCKn rising edge clock 111 CTCKn falling edge clock These three bits are used to select the clock source for the CTMn The external pin clock source can be chosen to be active on the rising or falling edge The clock source fSYS is the system clock while fH and fSUB are other internal clocks the details of which can be found in the osci...

Page 64: ...itched off before any changes are made to the CTnM1 and CTnM0 bits In the Timer Counter Mode the CTMn output pin state is undefined Bit 5 4 CTnIO1 CTnIO0 Select CTMn external pin CTPn function Compare Match Output Mode 00 No change 01 Output low 10 Output high 11 Toggle output PWM Output Mode 00 PWM output inactive state 01 PWM output active state 10 PWM output 11 Undefined Timer Counter Mode Unus...

Page 65: ...control 0 Non invert 1 Invert This bit controls the polarity of the CTPn output pin When the bit is set high the CTMn output pin will be inverted and not inverted when the bit is zero It has no effect if the CTMn is in the Timer Counter Mode Bit 1 CTnDPX CTMn PWM duty period control 0 CCRP period CCRA duty 1 CCRP duty CCRA period This bit determines which of the CCRA and CCRP registers are used fo...

Page 66: ...an be cleared by three methods These are a counter overflow a compare match from Comparator A and a compare match from Comparator P When the CTnCCLR bit is low there are two ways in which the counter can be cleared One is when a compare match from Comparator P the other is when the CCRP bits are all zero which allows the counter to overflow Here both CTMnAF and CTMnPF interrupt request flags for C...

Page 67: ...re zero then no pin change will take place Counter Value 0x3FF CCRP CCRA CTnON CTnPAU CTnPOL CCRP Int flag CTMnPF CCRA Int flag CTMnAF CTMn O P Pin Time CCRP 0 CCRP 0 Counter overflow CCRP 0 Counter cleared by CCRP value Pause Resume Stop Counter Restart CTnCCLR 0 CTnM 1 0 00 Output pin set to initial Level Low if CTnOC 0 Output Toggle with CTMnAF flag Note CTnIO 1 0 10 Active High Output select H...

Page 68: ...ected by CTMnAF flag Remains High until reset by CTnON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when CTnPOL is high CTMnPF not generated No CTMnAF flag generated on CCRA overflow Output does not change CTnCCLR 1 CTnM 1 0 00 CCRA Int flag CTMnAF CCRP Int flag CTMnPF Compare Match Output Mode CTnCCLR 1 n 0 1 Note 1 With CTnCCLR 1 a Comparato...

Page 69: ...egisters are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the CTnDPX bit in the CTMnC1 register The PWM waveform frequency and duty cycle can therefore be controlled by the valu...

Page 70: ... set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts when CTnPOL 1 PWM Period set by CCRP CTMn O P Pin CTnOC 0 CCRA Int flag CTMnAF CCRP Int flag CTMnPF CTnDPX 0 CTnM 1 0 10 PWM Output Mode CTnDPX 0 n 0 1 Note 1 Here CTnDPX 0 Counter cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when CTnIO 1 0 00...

Page 71: ...r Reset when CTnON returns high PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin shared function Output Inverts when CTnPOL 1 PWM Period set by CCRA CTMn O P Pin CTnOC 0 CTnDPX 1 CTnM 1 0 10 PWM Output Mode CTnDPX 1 n 0 1 Note 1 Here CTnDPX 1 Counter cleared by CCRA 2 A counter clear sets the PWM Period 3 The internal PWM function continues even when CTnIO 1 0 00 or ...

Page 72: ...AINS0 bits together with the SACS3 SACS0 bits When the external analog signal is to be converted the corresponding pin shared control bits should first be properly configured and then desired external channel input should be selected using the SAINS3 SAINS0 and SACS3 SACS0 bits Note that when the internal analog signal is to be converted the external channel input signal will automatically be disc...

Page 73: ... 6 5 4 3 2 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A D Converter Data Registers A D Converter Control Registers SADC0 SADC1 SADC2 To control the function and operation of the A D converter three control registers known as SADC0 SADC2 are provided These 8 bit registers define functions such as the selection of which analog signal is connec...

Page 74: ...ol 0 Disable 1 Enable This bit controls the A D internal function This bit should be set to one to enable the A D converter If the bit is set low then the A D converter will be switched off reducing the device power consumption When the A D converter function is disabled the contents of the A D data register pair known as SADOH and SADOL will be unchanged Bit 4 ADRFS A D converter data format sele...

Page 75: ...nal input External analog channel input ANn When the internal analog signal is selected to be converted the external channel signal input will automatically be switched off regardless of the SACS field value Bit 3 Unimplemented read as 0 Bit 2 0 SACKS2 SACKS0 A D conversion clock source select 000 fSYS 001 fSYS 2 010 fSYS 4 011 fSYS 8 100 fSYS 16 101 fSYS 32 110 fSYS 64 111 fSYS 128 These three bi...

Page 76: ...o exceed the value of the selected reference voltage VREF In addition the A D converter also has a VREFI pin which is one of PGA inputs for A D converter reference To select this PGA input signal the PGAIS bit in the SADC2 register must be cleared to zero and the relevant pin shared control bits should be properly configured However the PGA input can be also supplied from the internal independent ...

Page 77: ... 1 output voltage 1010 1011 xxxx GND Reserved connected to ground x Don t care A D Converter Input Signal Selection A D Converter Operation The START bit in the SADC0 register is used to start the AD conversion When the microcontroller sets this bit from low to high and then low again an analog to digital conversion cycle will be initiated The ADBZ bit in the SADC0 register is used to indicate whe...

Page 78: ...us applications it is therefore recommended that the ADCEN is set low to reduce power consumption when the A D converter function is not being used Conversion Rate and Timing Diagram A complete A D conversion contains two parts data sampling and data conversion The data sampling which is defined as tADS takes 4 A D clock cycles and the data conversion takes 12 A D clock cycles Therefore a total of...

Page 79: ... SAINS bit field should be properly configured and then the external channel input will automatically be disconnected regardless of the SACS bit field value After this step go to Step 6 Step 6 Select the reference voltage source by configuring the SAVRS1 SAVRS0 bits in the SADC2 register Select the PGA input signal and the desired PGA gain and enable the PGA if the PGA output voltage VR is selecte...

Page 80: ... VREF 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A D converter Except for the digitised zero value the subsequent digitised values will change at a point 0 5 LSB below where they would change without the offset and the last full scale digitised value will change at a point 1 5 LSB below the VREF level Note that here the ...

Page 81: ... fSYS 8 as A D clock and A D input mov SADC1 a signal comes from external channel mov a 00H select VDD as the A D reference voltage source mov SADC2 a mov a 0c0H setup PAS1 to configure pin AN0 mov PAS1 mov a 20h enable A D converter select default data format and connect AN0 channel to A D converter mov SADC0 a start_conversion clr START high pulse on START bit to initiate conversion set START re...

Page 82: ...th After the current is converted and amplified to a specific voltage level it will be compared with a reference voltage provided by the 12 bit OCP D A Converter n The OCP Operational Amplifier n and the OCP Comparator n can be configured to operate in the normal operating mode or input offset calibration mode determined by the OnOFM bit in the OPnVOS register and the CnOFM bit in the CMPnVOS regi...

Page 83: ...dependent D A converter Combine to a function of operational amplifier and comparator the operational amplifier amplifies a signal and then the comparator compares it with the external signals 1 0 ON OFF Independent operational amplifier Combine to an over voltage protection function of D A converter and comparator 1 1 ON ON Combine to a complete over current protection function of operational amp...

Page 84: ... D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 OCP D A Converter n output control code low byte Writing this register will only write the data to a shadow buffer and writing the DAnH register will simultaneously copy the shadow buffer data to the DAnL register OCP D A Converter n Output D A Converter n reference voltage 212 D 11 0 DACnC Register Bit 7 6 5 4 3 2 1 0 Na...

Page 85: ...bration procedures Bit 6 OPnEN OCP Operational Amplifier n enable or disable control bit 0 Disable 1 Enable Bit 5 2 Unimplemented read as 0 Bit 1 0 OPnBW1 OPnBW0 OCP Operational Amplifier n bandwidth control bits Refer to Operational Amplifier Electrical Characteristics for details OPnVOS Register Bit 7 6 5 4 3 2 1 0 Name OnOFM OnRSP OnOF5 OnOF4 OnOF3 OnOF2 OnOF1 OnOF0 R W R W R W R W R W R W R W ...

Page 86: ...bit is used to control the OCP Comparator n output polarity If the bit is zero then the OCP Comparator n output bit CMPnO will reflect the non inverted output condition of the OCP Comparator n If the bit is high the OCP Comparator n output bit will be inverted Bit 4 CMPnO OCP Comparator n output bit If CnPOL 0 0 CMPnP CMPnN 1 CMPnP CMPnN If CnPOL 1 0 CMPnP CMPnN 1 CMPnP CMPnN This bit stores the O...

Page 87: ...ut selection by configuring the OnRSP or CnRSP bit Note that as the OCP Operational Amplifier n or the OCP Comparator n inputs are pin shared with I O pins they should be configured as the OCP Operational Amplifier n inputs or the OCP Comparator n inputs first The following procedures use the positive input pins as reference input for example Operational Amplifier Input Offset Calibration Step 1 S...

Page 88: ...Detector LVD The device has a Low Voltage Detector function also known as LVD This enabled the device to monitor the power supply voltage VDD and provide a warning signal should it fall below a certain level This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages as it allows an early warning battery low signal to be generat...

Page 89: ...When the device is in the SLEEP mode the low voltage detector will be disabled even if the LVDEN bit is high After enabling the Low Voltage Detector a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit Note also that as the VDD voltage may rise and fall rather slowly at the voltage nears that of VLVD there may be multiple bit LVDO transitions VDD LVDEN LV...

Page 90: ... registers falls into three categories The first is the INTC0 INTC2 registers which setup the primary interrupts the second is the MFI0 MFI1 registers which setup the Multi function interrupts Finally there is an INTEG register to setup the external interrupt trigger edge type Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to ind...

Page 91: ...ster Bit 7 6 5 4 3 2 1 0 Name INT0F OCP1F OCP0F INT0E OCP1E OCP0E EMI R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 INT0F INT0 interrupt request flag 0 No request 1 Interrupt request Bit 5 OCP1F Over Current Protection 1 interrupt request flag 0 No request 1 Interrupt request Bit 4 OCP0F Over Current Protection 0 interrupt request flag 0 No request 1 Interru...

Page 92: ...Time Base 1 interrupt control 0 Disable 1 Enable Bit 2 TB0E Time Base 0 interrupt control 0 Disable 1 Enable Bit 1 MF1E Multi function interrupt 1 control 0 Disable 1 Enable Bit 0 MF0E Multi function interrupt 0 control 0 Disable 1 Enable INTC2 Register Bit 7 6 5 4 3 2 1 0 Name LVF INT1F DEF ADF LVE INT1E DEE ADE R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 LVF LVD interrupt reque...

Page 93: ...est flag 0 No request 1 Interrupt request Bit 3 2 Unimplemented read as 0 Bit 1 CTM0AE CTM0 Comparator A match interrupt control 0 Disable 1 Enable Bit 0 CTM0PE CTM0 Comparator P match interrupt control 0 Disable 1 Enable MFI1 Register Bit 7 6 5 4 3 2 1 0 Name CTM1AF CTM1PF CTM1AE CTM1PE R W R W R W R W R W POR 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 CTM1AF CTM1 Comparator A match interrupt ...

Page 94: ...ated with a RETI which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred The various interrupt enable bits together with their associated request flags are shown in the accompanying diagrams with their order of priority Some interrupt sources have their own individual vector while...

Page 95: ...viced the OCPn interrupt flag OCPnF will be automatically cleared The EMI bit will also be automatically cleared to disable other interrupts External Interrupts The external interrupts are controlled by signal transitions on the pins INT0 and INT1 An external interrupt request will take place when the external interrupt request flags INT0F INT1F are set which will occur when a transition whose typ...

Page 96: ...eared to disable other interrupts However it must be noted that although the Multi function Interrupt flags will be automatically reset when the interrupt is serviced the request flags from the original source of the Multi function interrupts will not be automatically reset and must be manually reset by the application program Time Base Interrupts The function of the Time Base Interrupts is to pro...

Page 97: ...0ON Time Base 0 Control 0 Disable 1 Enable Bit 6 3 Unimplemented read as 0 Bit 2 0 TB02 TB00 Select Time Base 0 Time out Period 000 28 fPSC 001 29 fPSC 010 210 fPSC 011 211 fPSC 100 212 fPSC 101 213 fPSC 110 214 fPSC 111 215 fPSC TB1C Register Bit 7 6 5 4 3 2 1 0 Name TB1ON TB12 TB11 TB10 R W R W R W R W R W POR 0 0 0 0 Bit 7 TB1ON Time Base 1 Control 0 Disable 1 Enable Bit 6 3 Unimplemented read ...

Page 98: ... Voltage Detector function detects a low power supply voltage To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI and Low Voltage Interrupt enable bit LVE must first be set When the interrupt is enabled the stack is not full and a low voltage condition occurs a subroutine call to the LVD Interrupt vector will take place When the LVD Interfa...

Page 99: ... service routine is executed as only the Multi function interrupt request flag MFnF will be automatically cleared the individual request flag for the function needs to be cleared by the application program It is recommended that programs do not use the CALL instruction within the interrupt service subroutine Interrupts often occur in an unpredictable manner or need to be serviced immediately If on...

Page 100: ...uts a 2 5V bias voltage and the operational amplifier together with external resistors form an amplifier circuit By using these functions the AC waveform will be converted to a sine wave with a 2 5V zero point The peak to peak values can be obtained through continuous A D conversion during an AC cycle to convert the input output voltage AVR Zero Crossing Detection Operating Principle The AC input ...

Page 101: ...re Circuit Diagram 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 D D C C B B A A M M1 T NTC D1 1N4007 Q1 NPN R7 2K vcc O L C7 104 Q6 NPN P10 C5 220uF 2 3 1 Vin Vout GND U2 HT7550 1 C4 104 C1 104 C3 100uF vcc 5V Q5 NPN Q4 NPN Q3 NPN Q2 NPN RL1 5V 1 2 3 4 5 6 7 10 11 13 12 14 AN3 15 PA5 16 17 18 21 22 23 24 OPA0O OPA0N OPA0P BUF_OUT0 OPA1P OPA1N OPA1O VDD VSS PA2 PA0 AN5 PB3 PB4 PB6 PB5 PA7 PA6 PB7 PC0 PB0 8 9 AN...

Page 102: ...ycle to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is involved then only one c...

Page 103: ... instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined by the condition of c...

Page 104: ...te Z C AC OV DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data Memory 1Note Z AND A x Logical AND immediate...

Page 105: ... and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table specific page to TBLH and Data Memory 2Note None TABRDC m Read table current page to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None Miscellaneous NOP No operation 1 None CLR m Clear Data Memory 1Note None SET m Set Data Memory 1Note None...

Page 106: ...or and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C AND A m Logical AND Data Memory to ACC Description Data in...

Page 107: ...PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect Repetitively executing this instruction without alternately executing CLR WDT2 will have no...

Page 108: ...his instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H or m ACC 66H Affected flag s C DEC m Decrement Data Memory Description Data in the specified Data Memory is decremented by 1 Operation m m 1 Affected flag s Z DECA m Decrement Data Memory with result in ACC Description Data in ...

Page 109: ... ACC Affected flag s None NOP No operation Description No operation is performed Execution continues with the next instruction Operation No operation Affected flag s None OR A m Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation The result is stored in the Accumulator Operation ACC ACC OR m Affected flag s Z OR A x...

Page 110: ... Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 m 7 Affected flag s None RLC m Rotate Data Memory left through Carry Description The contents of the specified Data Memory ...

Page 111: ...act Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Accumulator Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is positive or zero the C flag will be set to 1 Operation ACC ACC m C Affected flag s OV Z...

Page 112: ... program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SIZA m Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped The result is stored in the Accumulator but the specified Data Memory contents remain unchanged As th...

Page 113: ...e interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it i...

Page 114: ...a Memory Description The low byte of the program code last page addressed by the table pointer TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None XOR A m Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation Th...

Page 115: ...ntervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Package Information include Outline Dimensions Product Tape and Reel Specifications The Operation Instruction of Packing Materials...

Page 116: ...ns in inch Min Nom Max A 0 228 0 236 0 244 B 0 146 0 154 0 161 C 0 009 0 012 C 0 382 0 390 0 398 D 0 069 E 0 032 BSC F 0 002 0 009 G 0 020 0 031 H 0 008 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 5 80 6 00 6 20 B 3 70 3 90 4 10 C 0 23 0 30 C 9 70 9 90 10 10 D 1 75 E 0 80 BSC F 0 05 0 23 G 0 50 0 80 H 0 21 0 25 α 0 8 ...

Page 117: ...ions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 606 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 α 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 50 BSC C 0 31 0 51 C 15 40 BSC D 2 65 E 1 27 BSC F 0 10 0 30 G 0 40 1 27 H 0 20 0 33 α 0 8 ...

Page 118: ...sions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 341 BSC D 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 00 BSC B 3 90 BSC C 0 20 0 30 C 8 66 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 α 0 8 ...

Page 119: ...d solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holtek reserves...

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