Rev. 1.40
130
March 29, 2019
Rev. 1.40
131
March 29, 2019
HT45F23A/HT45F24A
TinyPower
TM
Flash MCU with OPA & Comparators
HT45F23A/HT45F24A
TinyPower
TM
Flash MCU with OPA & Comparators
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced,
however, once an interrupt request flag is set, it will remain in this condition in the INTC0,
INTC1,MFIC0 and MFIC1 registers until the corresponding interrupt is serviced or until the request
flag is cleared by the application program.
It is recommended that programs do not use the “CALL Subroutine” instruction within the interrupt
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately
in some applications. If only one stack is left and the interrupt is not well controlled, the original
control sequence will be damaged once a “CALL subroutine” is executed in the interrupt subroutine.
All of these interrupts have the capability of waking up the processor when in the Power Down
Mode. Only the Program Counter is pushed onto the stack. If the contents of the status or other
registers are altered by the interrupt service program, which may corrupt the desired control
sequence, then the contents should be saved in advance.
Buzzer
Operating in a similar way to the Programmable Frequency Divider, the Buzzer function provides
a means of producing a variable frequency output, suitable for applications such as Piezo-buzzer
driving or other external circuits that require a precise frequency generator. The BZ and BZ pins
form a complimentary pair, and are pin-shared with I/O pins, PA6 and PA7. A BPCTL register is
used to select
from one of three buzzer options. The first option is for both pins PA6 and PA7 to be
used as normal
I/Os, the second option is for both pins to be configured as BZ and
BZ buzzer pins,
the third option selects only the PA6 pin to be used as a BZ buzzer pin with the PA7 pin retaining its
normal I/O pin function. Note that the BZ pin is the inverse of the BZ pin which together generate a
differential output which can supply more power to connected interfaces such as buzzers.
The buzzer is driven by the internal clock source, f
TB
, which then passes through a divider, the
division ratio of which is selected by BPCTL register to provide a range of buzzer frequencies from
f
TB
/2
2
to f
TB
/2
9
. The clock source that generates f
TB
, which in turn controls the buzzer frequency,
can originate from three different sources, the LXT oscillator, the LIRC oscillator or the System
oscillator/4, the choice of which is determined by the f
TB
clock source option. Note that the buzzer
frequency is controlled by BPCTL register, which select the source clock for the internal clock f
TB
.
Buzzer Function
If the BPCTL options have selected both pins PA6 and PA7 to function as a BZ and BZ
complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins
must be setup as outputs by setting bits PAC6 and PAC7 of the PAC port control register to zero.
The PA6 data bit in the PA data register must also be set high to enable the buzzer outputs, if set low,
both pins PA6 and PA7 will remain low. In this way the single bit PA6 of the PA register can be used
as an on/off control for both the BZ and BZ buzzer pin outputs. Note that the PA7 data bit in the PA
register has no control over the BZ buzzer pin PA7.