Holtek HT45F23A Manual Download Page 115

Page: 115 / 156

Rev. 1.40

114

March 29, 2019

Rev. 1.40

115

March 29, 2019

HT45F23A/HT45F24A

TinyPower

Flash MCU with OPA & Comparators

HT45F23A/HT45F24A

TinyPower

Flash MCU with OPA & Comparators

OPA2 switch control:
The following table illustrates the relationship between OPA2 control register settings and the
switches:

OPA2 Control Bits in OPA2C0, OPA2C1, OPA2C2

Switch Description

Results

A2PS A2NS

A2PSEL1

A2PSEL0

A1O2A2P A1O2A2N

PGAEN

A2O2N S4D S5D S6/7D S8D S9D S11D

S12D~

S14D

OPA2

connections

On On

Off

Off Off

Off

Normal mode,

Input=A2N, A2P

Off On

Off

Off Off

Off

S12D

Input=A2N, VH1

Off On

Off

Off Off

Off

S13D

Input=A2N, VM

Off On

Off

Off Off

Off

S14D

Input=A2N, VL1

Off On

Off

Off Off

Off

Input=A2N, A1E

On Off

Off

On Off

Off

Input=A1E, A2P

On On

Off Off

Off

Input=A2N, A2P

On Off

Off Off

Off

Input=A2N, A2P

On Off

Off

Off On

Off

Input=A2P,

OPA2 as buffer

Off Off

Off

Off Off

Off

S12D

Input=VH1,

OPA2 as buffer

Off Off

Off

Off Off

Off

S13D

Input=VM,

OPA2 as buffer

Off Off

Off

Off Off

Off

S14D

Input=VL1,

OPA2 as buffer

OPA2 & I/O status description:
The following table illustrates the OPA2 & I/O settings.

A2EN PGAEN

A2NS A2PS

Description

PA5 and PA6 and PA7 are I/Os

PA5 and PA6 are I/Os. PA7 is OPA2 A2E output

PA6 is I/O. PA5 is OPA2 A2P input, PA7 is OPA2 A2E output

PA5 is I/O. PA6 is OPA2 A2N input, PA7 is OPA2 A2E output

PA5 is OPA2 A2P input and PA6 is OPA2 A2N input, PA7 is OPA2 A2E output

PA5 is I/O. PA6 is OPA2 A2N input, PA7 is OPA2 A2E output

PA5 is OPA2 A2P input and PA6 is OPA2 A2N input, PA7 is OPA2 A2E output

PA5 is I/O. PA6 is OPA2 A2N input and bypass R1 (10kΩ), PA7 is OPA2 A2E output

PA5 is OPA2 A2P input and PA6 is OPA2 A2N input and bypass R1 (10kΩ), PA7 is

OPA2 A2E output

Summary of Contents for HT45F23A

Page 1: ...TinyPowerTM Flash MCU with OPA Comparators HT45F23A HT45F24A Revision V1 40 Date March 29 2019 ...

Page 2: ... Characteristics 17 LDO 2 4V 17 LDO 3 3V 18 Power on Reset Characteristics 18 System Architecture 19 Clocking and Pipelining 19 Program Counter 20 Stack 21 Arithmetic and Logic Unit ALU 21 Flash Program Memory 22 Structure 22 Special Vectors 22 Look up Table 23 Table Program Example 24 In Circuit Programming 25 RAM Data Memory 26 Structure 27 Special Function Registers 27 Indirect Addressing Regis...

Page 3: ... 39 External 32 768kHz Crystal Oscillator LXT 39 LXT Oscillator Low Power Function 40 Internal 32kHz Oscillator LIRC 40 Supplementary Oscillators 40 Operating Modes and System Clocks 41 System Clocks 41 System Operation Modes 41 Control Register 44 Fast Wake up 45 Operating Mode Switching and Wake up 46 Standby Current Considerations 50 Wake up 51 Programming Considerations 51 Watchdog Timer 52 Wa...

Page 4: ... PWM Operation 74 6 2 PWM Mode 75 7 1 PWM Mode 76 PWM Output Control 77 Analog to Digital Converter 78 A D Overview 78 A D Converter Register Description 79 A D Converter Data Registers ADRL ADRH 79 A D Converter Control Registers ADCR ACSR ADPCR 79 A D Operation 83 A D Input Pins 84 Summary of A D Conversion Steps 85 Programming Considerations 86 A D Transfer Function 86 A D Programming Example 8...

Page 5: ...121 Interrupt Register 121 Interrupt Operation 121 Interrupt Priority 122 External Interrupt 125 External Peripheral Interrupt 127 Timer Event Counter Interrupt 127 SPI I2 C Interface Interrupt 128 Multi function Interrupt 128 A D Interrupt 128 Time Base Interrupt 129 Comparator Interrupt 130 EEPROM Interrupt 130 LVD Interrupt 130 Interrupt Wake up Function 130 Programming Considerations 131 Buzze...

Page 6: ...8 Logical and Rotate Operation 139 Branches and Control Transfer 139 Bit Operations 139 Table Read Operations 139 Other Operations 139 Instruction Set Summary 140 Table Conventions 140 Instruction Definition 142 Package Information 151 16 pin NSOP 150mil Outline Dimensions 152 20 pin SSOP 150mil Outline Dimensions 153 24 pin SSOP 150mil Outline Dimensions 154 28 pin SSOP 150 mil Outline Dimensions...

Page 7: ...duce power consumption Oscillator types External Crystal HXT External 32 768kHz Crystal LXT External RC ERC Internal RC HIRC Internal 32kHz RC LIRC External Clock EC Multi mode operation Normal Slow Idle and Sleep Fully integrated internal 32kHz 910kHz 2MHz 4MHz and 8MHz oscillator requires no external components Externally supplied system clock option All instructions executed in one or two machi...

Page 8: ...e Timer Event Counter with overflow interrupt and Single 16 bit programmable Timer Event Counter with overflow interrupt function Dual Time Base functions Serial Interfaces Module SIM for SPI or I2 C Dual Comparator functions Dual Operational Amplifiers functions Operational Amplifier output to internal two channel 12 bit ADC function Multi channel 12 bit ADC Up to 2 channel 8 bit PWM 12 bit Audio...

Page 9: ...hdog Timer Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments A full choice of internal external low and high speed oscillator functions are provided including fully integrated system oscillators which require no external components for their implementation The unique Ho...

Page 10: ...ram Memory EEPROM Data Memory Flash EEPROM Programming Circuitry Time Base PFD Buzzer Driver Low Voltage Reset Watchdog Timer Low Voltage Detect Interrupt Controller Reset Circuit External Oscillators 12 bit A D Converter RAM Data Memory ICP Internal RC Oscillators Comparators PWM Generator D A Converter I O SIM Timers OPAs LDO Pin Assignment ...

Page 11: ... TC1 ST External Timer 1 clock input PA5 A2P PFD PA5 PAPU PAWU ST CMOS General purpose I O Register enabled pull up wake up A2P OPA2C1 OPAI OPA2 non inverting input pin PFD MISC CMOS PFD output PA6 A2N BZ PA6 PAPU PAWU ST CMOS General purpose I O Register enabled pull up wake up A2N OPA2C1 OPAI OPA2 inverting input pin BZ BPCTL CMOS Buzzer output PA7 A2E BZ PA7 PAPU PAWU ST CMOS General purpose I ...

Page 12: ...erence input VCAP LDOC LDO output capacitor pin Connect a 0 1µF capacitor SCOM1 LCDC SCOM Software controlled 1 2 bias LCD COM PC5 PWM0 C1N SCOM2 PC5 PCPU ST CMOS General purpose I O Register enabled pull up PWM0 BPCTL CMOS PWM0 output pin C1N CMP1C1 CMPI Comparator 1 inverting input pin SCOM2 LCDC SCOM Software controlled 1 2 bias LCD COM PC6 PWM1 C2P SCOM3 PC6 PCPU ST CMOS General purpose I O Re...

Page 13: ...HXT ERC HIRC 2 2 5 5 V fSYS 2MHz HXT ERC HIRC 2 2 5 5 V fSYS 4MHz HXT ERC HIRC EC 2 2 5 5 V fSYS 8MHz HXT ERC HIRC EC 3 3 5 5 V IDD1 Operating Current HXT ERC 3 3V No load fSYS fM 455kHz ADC off LVR off Comparator off OPAs off 70 110 µA Operating Current HXT ERC No load fSYS fM 455kHz ADC off LVR on Comparator on OPAs off 100 150 µA IDD2 Operating Current ERC HIRC 3 3V No load fM 910kHz fSYS fSLOW...

Page 14: ...00 450 µA 5V 680 1020 µA IDD12 Operating Current Slow Mode fM 8MHz HXT ERC HIRC 3V No load fSYS fSLOW 4MHz ADC off 450 800 µA 5V 1000 1500 µA IDD13 Operating Current fSYS LXT note 1 or LIRC 3V No load WDT off ADC off 10 20 µA 5V 20 35 µA ISTB1 Standby Current Sleep fSYS fSUB fS fWDT off 3V No load system HALT WDT off 0 1 1 0 µA 5V 0 2 2 0 µA ISTB2 Standby Current Sleep fSYS Off fS On fWDT fSUB LXT...

Page 15: ...50 kΩ AVDD A D Converter Operating Voltage 2 7 5 5 V VAD A D Input Voltage 0 VREF V VREF A D Input Reference Voltage Range AVDD 5V 2 VDD V DNL ADC Differential Non Linearity 3V VREF VDD tAD 1µs 1 2 LSB 5V INL ADC Integral Non Linearity 3V VREF VDD tAD 1µs 2 4 LSB 5V IADC Additional Power Consumption if A D Converter is Used 3V 0 5 1 0 mA 5V 1 5 3 0 mA VBG Bandgap Reference with Buffer voltage 3 1 ...

Page 16: ... tLVR Low Voltage width to Reset 60 120 240 µs tLVD Low Voltage width to Interrupt 60 120 240 µs tLVDS LVDO Stable Time 5V LVR disable LVD enable VBG is ready 100 µs tRSTD System Reset Delay Time Power on Reset 100 ms tSST1 System start up timer period W O fast start up of HXT TBC Power up or wake up from Sleep mode 1024 tSYS note 1 tSST2 System start up timer period of ERC HIRC EC Power up or wak...

Page 17: ...L 1MΩ CL 100pF 1 2 MHz Comparator Electrical Characteristics Ta 25 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VDDC Comparator Operating Voltage 2 2 5 5 V IDDC Comparator Operating Current 3V 20 40 µA 5V 30 60 µA VCPOS1 Comparator Input Offset Voltage 5V CxOF 4 0 10000 10 10 mV VCPOS2 Comparator Input Offset Voltage 5V By calibration 4 4 mV VCM Comparator Common Mode Voltage...

Page 18: ...F 200 1100 µA tSTART LDO Turn On Stable Time 5V VCAP 10uF 1600 ms Note 1 This LDO can provide stable power supply for PIR sensor with a 10µF cap 2 The VREF pin should be connected to 10µF for ADC reference voltage and 10µF for PIR sensor Power on Reset Characteristics Ta 25 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VPOR VDD Start Voltage to Ensure Power on Reset 100 mV RRV...

Page 19: ...essing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I O and A D control system with maximum reliability and flexibility This makes the devices suitable for low cost high volume production for controller applications Clocking and Pipelining The main system clock derived from either a Crystal ...

Page 20: ... requiring jumps to non consecutive addresses such as a jump instruction a subroutine call interrupt or reset etc the microcontroller manages program control by loading the required address into the Program Counter For conditional skip instructions once the condition has been met the next instruction which has already been fetched during the present instruction execution is discarded and a dummy c...

Page 21: ...sily However when the stack is full a CALL subroutine instruction can still be executed which will result in a stack overflow Precautions should be taken to avoid such cases which might cause unpredictable program branching P r o g r a m C o u n t e r S t a c k L e v e l 1 S t a c k L e v e l 2 S t a c k L e v e l 3 S t a c k L e v e l 6 P r o g r a m M e m o r y T o p o f S t a c k S t a c k P o ...

Page 22: ...et is initiated the program will jump to this location and begin execution Location 004H This vector is used by the external interrupt 0 If the external interrupt pin receives an active edge the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full Location 008H This vector is used by the external interrupt 1 If the external interrupt...

Page 23: ...e the look up table the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register TBLP and TBHP These registers define the total address of the look up table After setting up the table pointer the table data can be retrieved from the Program Memory using the TABRDC m or TABRDL m instructions respectively When the instruction is execu...

Page 24: ... table pointer is setup here to have an initial value of 06H This will ensure that the first data read from the data table will be at the Program Memory address 0F06H or 6 locations after the start of the last page Note that the value for the table pointer is referenced to the first address of the present page if the TABRDC m instruction is being used The high byte of the table data which in this ...

Page 25: ...enience Holtek has provided a means of programming the microcontroller in circuit using a 5 pin interface This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un programmed microcontroller and then programming or upgrading the program at a later stage This enables product manufacturers to easily keep their manufactured products suppli...

Page 26: ... P r o g r a m m i n g P i n s Note may be resistor or capacitor The resistance of must be greater than 1kΩ or the capacitance of must be less than 1nF RAM Data Memory The Data Memory is a volatile area of 8 bit wide RAM internal memory and is the location where temporary information is stored Data Memory Structure Note Most of the Data Memory bits can be directly manipulated using the SET m i and...

Page 27: ...gister at address 40H which is only accessible in Bank 1 Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value The start address of the Data Memory is the address 00H All microcontroller programs require an area of read write memory where temporary data can be stored and retrieved for use later It is this area of RAM memory that is known as ...

Page 28: ...ted in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data When any operation to the relevant Indirect Addressing Registers is carried out the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer MP0 together with Indirect Addressing Register IAR0 are used...

Page 29: ...y is not affected by the bank selection which means that the Special Function Registers can be accessed from within either Bank 0 or Bank 1 Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer BP Register Bit 7 6 5 4 3 2 1 0 Name DMBP0 R W R W POR 0 Bit 7 1 Unimplemented read as 0 Bit 0 DMBP0 Select Data Memory Banks 0 Bank 0...

Page 30: ...data instruction has been executed Note that the lower order table data byte is transferred to a user defined location Status Register STATUS This 8 bit register contains the zero flag Z carry flag C auxiliary carry flag AC overflow flag OV power down flag PDF and watchdog time out flag TO These arithmetic logical operation and system management flags are used to record the status and operation of...

Page 31: ...ow flag 0 no overflow 1 an operation results in a carry into the highest order bit but not a carry out of the highest order bit or vice versa Bit 2 Z Zero flag 0 The result of an arithmetic or logical operation is not zero 1 The result of an arithmetic or logical operation is zero Bit 1 AC Auxiliary flag 0 no auxiliary carry 1 an operation results in a carry out of the low nibbles in addition or n...

Page 32: ...rectly accessible in the same way as the other types of memory Instead it has to be accessed indirectly through the EEPROM control registers EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory These are the address register EEA the data register EED and a single control register EEC As both the EEA and EED registers are located in Bank 0 they can be di...

Page 33: ...h by the application program will activate a write cycle This bit will be automatically reset to zero by the hardware after the write cycle has finished Setting this bit high will have no effect if the WREN has not first been set high Bit 1 RDEN Data EEPROM Read Enable 0 Disable 1 Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried o...

Page 34: ...ll have been written into the EEPROM Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt When the write cycle terminates the WR bit will be automatically cleared to zero by the microcontroller informing the user that the data has been written to the EEPROM The application program can therefore poll the WR ...

Page 35: ...ote that the devices should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete Otherwise the EEPROM read or write operation will fail Programming Examples Reading data from the EEPROM polling method MOV A EEPROM_ADRES user defined address MOV EEA A MOV A 040H setup memory pointer MP1 MOV MP1 A MP1 points to EEC register MOV A 01H setup Bank Pointer MOV BP...

Page 36: ... The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements while the opposite is of course true for the lower frequency oscillators With the capability of dynamically switching between fast and slow system clock the devices have the flexibility to optimize the performance power ratio a feature especially important in power sensitive...

Page 37: ...rystal Ceramic Oscillator HXT The External Crystal Ceramic System Oscillator is one of the high frequency oscillator choices which is selected via configuration option For most crystal oscillator configurations the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation without requiring external capacitors However for some crystal typ...

Page 38: ...uence over the frequency and is connected for stability purposes only Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage temperature and process variations on the oscillation frequency are minimised As a resistance frequency reference point it can be noted that with an exte...

Page 39: ... of 910kHz 2MHz 4MHz or 8MHz will have a tolerance within 2 Note that if this internal system clock option is selected as it requires no external pins for its operation I O pins PC0 and PC1 are free for use as normal I O pins External 32 768kHz Crystal Oscillator LXT The External 32 768kHz Crystal System Oscillator is one of the low frequency oscillator choices which is selected via configuration ...

Page 40: ... placed into the Low power mode by setting the LXTLP bit high The oscillator will continue to run but with reduced current consumption as the higher current consumption is only required during the LXT oscillator start up In power sensitive applications such as battery applications where power consumption must be kept to a minimum it is therefore recommended that the application program sets the LX...

Page 41: ...gh speed system clock can be sourced from either an HXT ERC EC or HIRC oscillator selected via a configuration option The low speed system clock source can be sourced from internal clock fL If fL is selected then it can be sourced by either the LXT or LIRC oscillators selected via a configuration option The other choice which is a divided version of the high speed system oscillator has a range of ...

Page 42: ...tched to fL from fH the high speed oscillation will stop to conserve the power Thus there is no fH fH 64 for peripheral circuit to use Operation Mode Description CPU fSYS fSUB fS fTBC NORMAL Mode On fH fH 64 On On On SLOW Mode On fL On On On IDLE0 Mode Off Off On On Off On IDLE1 Mode Off On On On On SLEEP0 Mode Off Off Off Off Off SLEEP1 Mode Off Off On On Off ...

Page 43: ...LEEP1 Mode The SLEEP Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is low In the SLEEP1 mode the CPU will be stopped However the fSUB and fS clocks will continue to operate if the LVDEN is 1 or the Watchdog Timer function is enabled and if its clock source is chosen via configuration option to come from the fSUB IDLE0 Mode The IDLE0 Mode is entered...

Page 44: ... system clock to provide a faster wake up time as the fSUB clock is available Bit 3 LTO Low speed system oscillator ready flag 0 Not ready 1 Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake up has occurred The flag will be low when in the SLEEP0 Mode but after a wake up has occurred the flag will ...

Page 45: ...he Fast Wake up function is fSUB the Fast Wake up function is only available in the SLEEP1 and IDLE0 modes When the devices are woken up from the SLEEP0 mode the Fast Wake up function has no effect because the fSUB clock is stopped The Fast Wake up enable disable function is controlled using the FSTEN bit in the SMOD register If the HXT oscillator is selected as the NORMAL Mode system clock and if...

Page 46: ...witching from the NORMAL SLOW Modes to the SLEEP IDLE Modes is executed via the a HALT instruction When a HALT instruction is executed whether the devices enter the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the WDTC register When the HLCLK bit switches to a low level which implies that clock source is switched from the high speed...

Page 47: ...LCLK bit to 0 and set the CKS2 CKS0 bits to 000 or 001 in the SMOD register This will then use the low speed system oscillator which will consume less power Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these oscillators to be...

Page 48: ...he NORMAL Mode where the high speed system oscillator is used the HLCLK bit should be set to 1 or HLCLK bit is 0 but CKS2 CKS0 is set to 010 011 100 101 110 or 111 As a certain amount of time will be required for the high frequency clock to stabilise the status of the HTO bit is checked The amount of time required for high speed system oscillator stabilization depends upon which high speed system ...

Page 49: ...clock will be stopped and the application program will stop at the HALT instruction but the WDT or LVD will remain with the clock source coming from the fSUB clock The Data Memory contents and registers will maintain their present condition The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock as the WDT is enabled The I O ports will maintain t...

Page 50: ...e devices to as low a value as possible perhaps only in the order of several micro amps except in the IDLE1 Mode there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised Special attention must be made to the I O pins on the devices All high impedance input pins must be connected to either a fixed high or low level as a...

Page 51: ...h woke up the devices will not be immediately serviced but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free The other situation is where the related interrupt is enabled and the stack is not full in which case the regular interrupt response takes place If an interrupt request flag is set high before entering the SLEEP or IDLE Mode the w...

Page 52: ...ons The LXT oscillator is supplied by an external 32 768kHz crystal The other Watchdog Timer clock source option is the fSYS 4 clock The Watchdog Timer clock source can originate from its own internal LIRC oscillator the LXT oscillator or fSYS 4 It is divided by a value of 213 to 220 using the WS2 WS0 bits in the WDTC register to obtain the required Watchdog Timer time out period Watchdog Timer Co...

Page 53: ...r normal program operation a Watchdog Timer time out will initialise devices reset and set the status bit TO However if the system is in the SLEEP or IDLE Mode when a Watchdog Timer time out occurs the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset Three methods can be adopted to clear the contents of the Watchdog Timer The first is an extern...

Page 54: ...nning the RES line is forcefully pulled low In such a case known as a normal operation reset some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high Another type of reset is when the Watchdog Timer overflows and resets the microcontroller All types of reset operations result in different reg...

Page 55: ...he microcontroller will begin normal operation The abbreviation SST in the figures stands for System Start up Timer For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference...

Page 56: ...configuration options Note tRSTD is power on delay typical time 100ms Low Voltage Reset Timing Chart Watchdog Time out Reset during Normal Operation The Watchdog time out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time out flag TO will be set to 1 WDT Time out Internal Reset tRSTD Note tRSTD is power on delay typical time 100ms WDT Time out Reset...

Page 57: ...h the various components of the microcontroller are affected after a power on reset occurs Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset WDT begins counting Timer Event Counter Timer Counter will be turned off Input Output Ports I O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stac...

Page 58: ... MFIC1 000 000 000 000 000 000 uuu uuu PA 1111 1111 1111 1111 1111 1111 u u u u u u u u PAC 1111 1111 1111 1111 1111 1111 u u u u u u u u PB 111 1111 111 1111 111 1111 uuu uuuu PB 1111 1111 1111 1111 1111 1111 u u u u u u u u PBC 111 1111 111 1111 111 1111 uuu uuuu PBC 1111 1111 1111 1111 1111 1111 u u u u u u u u PC 111 1111 111 1111 111 1111 uuu uuuu PC 1111 1111 1111 1111 1111 1111 u u u u u u ...

Page 59: ...x u u u u u u u u TMR1C 0000 1 0000 1 0000 1 uuuu u EEA x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u EED x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u EEC 0000 0000 0000 uuuu LCDC 000 0000 000 0000 000 0000 uuu uuuu LDOC 0 0000 0 0000 0 0000 u uuuu DACTRL 000 0 000 0 000 0 uuu u DAL 0000 0000 0000 uuuu DAH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u...

Page 60: ... as PAPU PBPU PCPU and PDPU located in the Data Memory The pull high resistors are implemented using weak PMOS transistors Port A Wake up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power a feature that is important for battery and other low power applications Various methods exist to wake up the microcontroller one of which is to change the logic co...

Page 61: ... disable 1 enable PAPUn PBPUn PCPUn Pull high function enable 0 disable 1 enable PACn PBCn PCCn I O type selection 0 output 1 input HT45F24A Register Name Bit 7 6 5 4 3 2 1 0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2...

Page 62: ...gram one of the first things to consider is port initialisation After a reset all of the I O data and port control registers will be set high This means that all I O pins will default to an input state the level of which depends on the other connected circuitry and whether pull high selections have been chosen If the port control registers PAC PDC are then programmed to setup some pins as outputs ...

Page 63: ...en the devices are in the SLEEP or IDLE Mode various methods are available to wake the devices up One of these is a high to low transition of any of the Port A pins Single or multiple pins on Port A can be setup to have this function In addition the Port B pins also provide Open Drain I O structure options which can be controlled by the specific register Generic Input Output Ports ...

Page 64: ...nal clock source can be chosen from a combination of internal clocks using a configuration option and the T1S bit in the TMR1C register An external clock source is used when the timer is in the event counting mode the clock source being provided on an external timer pin TC0 or TC1 depending upon which timer is used Depending upon the condition of the T0E or T1E bit each high to low or low to high ...

Page 65: ... is only carried out when a write to its associated high byte timer register namely TMR1H is executed On the other hand using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte timer register At the same time the data in the low byte buffer will be transferred into its associated low byte timer register For this reason the...

Page 66: ...e event count or pulse width measurement mode the active transition edge level type is selected by the logic level of bit 3 of the Timer Control Register which is known as T0E or T1E depending upon which timer is used An additional T1S bit in the TMR1C register is used to determine the clock source for Timer Event Counter 1 Configuring the Timer Mode In this mode the Timer Event Counter can be uti...

Page 67: ...bled by ensuring that the Timer Event Counter Interrupt Enable bit in the Interrupt Control Register INTC0 is reset to zero It should be noted that in the internal event counting mode even if the microcontroller is in the Power Down Mode the Timer Event Counter will continue to record externally changing logic events on the timer input pin As a result when the timer overflows it will generate a ti...

Page 68: ...Timer Event Counter which can now be read by the program therefore represents the length of the pulse received on the external timer pin As the enable bit has now been reset any further transitions on the external timer pin will be ignored Not until the enable bit is again set high by the program can the timer begin further pulse width measurements In this way single shot pulse measurements can be...

Page 69: ... signal is generated causing the PFD output to change state The timer will then be automatically reloaded with the preload register value and continue counting up For the PFD output to function it is essential that the corresponding bit of the Port A control register PAC bit 5 is setup as an output If setup as an input the PFD output will not function however the pin can still be used as a normal ...

Page 70: ...nal is from TC0 pin 10 timer mode 11 pulse width capture mode Bit 5 unimplemented read as 0 Bit 4 T0ON Timer Event Counter counting enable 0 disable 1 enable Bit 3 T0E Event counter active edge selection 0 count on raising edge 1 count on falling edge Pulse Width Capture active edge selection 0 start counting on falling edge stop on rasing edge 1 start counting on raising edge stop on falling edge...

Page 71: ...ounter active edge selection 0 count on raising edge 1 count on falling edge Pulse width capture active edge selection 0 start counting on falling edge stop on rasing edge 1 start counting on raising edge stop on falling edge Bit 2 0 unimplemented read as 0 MISC Register Bit 7 6 5 4 3 2 1 0 Name ODE3 ODE2 ODE1 ODE0 PFDSEL PFDEN R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 ODE3 PB3 Open Drain ...

Page 72: ...l generate an internal interrupt signal directing the program flow to the respective internal interrupt vector For the pulse width measurement mode the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin As this is an external event and not synchronized with the internal timer clock the mi...

Page 73: ...uction to enter the Power Down Mode Timer Program Example This program example shows how the Timer Event Counter registers are setup along with how the interrupts are enabled and managed Note how the Timer Event Counter is turned on by setting bit 4 of the Timer Control Register The Timer Event Counter can be turned off in a similar way by clearing the same bit This example program sets the Timer ...

Page 74: ...bdivision of the waveform into its sub modulation cycles is implemented automatically within the microcontroller hardware The PWM clock source is the system clock fSYS This method of dividing the original modulation cycle into a further 2 or 4 sub cycles enable the generation of higher PWM frequencies which allow a wider range of applications to be served The difference between what is known as th...

Page 75: ... duty cycle of the PWM waveform is divided into two groups The first group which consists of bit2 bit7 is denoted here as the DC value The second group which consists of bit0 bit1 is known as the AC value In the 6 2 PWM mode the duty cycle value of each of the four modulation sub cycles is shown in the following table Parameter AC 0 3 DC Duty Cycle Modulation cycle i i 0 3 i AC DC 1 64 i AC DC 64 ...

Page 76: ...all duty cycle of the PWM waveform is divided into two groups The first group which consists of bit1 bit7 is denoted here as the DC value The second group which consists of bit0 is known as the AC value In the 7 1 PWM mode the duty cycle value of each of the two modulation sub cycles is shown in the following table Parameter AC 0 1 DC Duty Cycle Modulation cycle i i 0 1 i AC DC 1 128 i AC DC 128 7...

Page 77: ...ue to the corresponding bit in the output data register PC 5 and PC 6 will enable the PWM data to appear on the pin Writing a zero value will disable the PWM output function and force the output low In this way the Port data output registers can be used as an on off control for the PWM function Note that if the BPCTL register has selected the PWM function but a high value has been written to its c...

Page 78: ...ing follow on benefits of lower costs and reduced component space requirements A D Overview The devices contain an 8 10 channel analog to digital converter which can directly interface to external analog signals such as that from sensors or other control signals and convert these signals directly into either a 12 bit digital value Part No Input Channels A D Channel Select Bits Input Pins HT45F23A ...

Page 79: ...erter Control Registers ADCR ACSR ADPCR To control the function and operation of the A D converter three control registers known as ADCR ACSR and ADPCR are provided These 8 bit registers define functions such as the selection of which analog channel is connected to the internal A D converter the digitised data format the A D clock source as well as controlling the start function and monitoring the...

Page 80: ...A D channel 000 AN0 001 AN1 010 AN2 011 AN3 100 AN4 101 AN5 110 AN6 connect Op Amp 1 output A1E 111 AN7 connect Op Amp 2 output A2E These are the A D channel select control bits As there is only one internal hardware A D converter each of the eight A D inputs must be routed to the internal converter using these bits HT45F24A Bit 7 6 5 4 3 2 1 0 Name START EOCB ACS3 ACS2 ACS1 ACS0 R W R W R R W R W...

Page 81: ...n the A D converter will be switched off reducing the devices power consumption As the A D converter will consume a limited amount of power even when not executing a conversion this may be an important consideration in power sensitive battery powered applications Note 1 it is recommended to set ADONB 1 before entering IDLE SLEEP Mode for saving power 2 ADONB 1 will power down the ADC module Bit 5 ...

Page 82: ...nput AN2 Bit 1 PCR1 Define PB4 is A D input or not 0 Not A D input 1 A D input AN1 Bit 0 PCR0 Define PB3 is A D input or not 0 Not A D input 1 A D input AN0 HT45F24A Bit 7 6 5 4 3 2 1 0 Name PCR7 PCR6 PCR5 PCR4 PCR3 PCR2 PCR1 PCR0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 PCR7 Define PD1 is A D input or not 0 Not A D input 1 A D input AN7 Bit 6 PCR6 Define PD0 is A D input or n...

Page 83: ...heck whether it has been cleared as an alternative method of detecting the end of an A D conversion cycle The clock source for the A D converter which originates from the system clock fSYS can be chosen to be either fSYS or a subdivided version of fSYS The division ratio value is determined by the ADCS2 ADCS0 bits in the ACSR register Although the A D clock source is determined by the system clock...

Page 84: ...ion will be selected and the other pin functions will be disabled automatically A D Input Pins The A D analog input pins are pin shared with the I O pins on Port B Port C and Port D as well as other functions The PCR7 PCR0 bits in the ADPCR register determine whether the input pins are setup as A D converter analog inputs or whether they have other functions If the PCR7 PCR0 bits for its correspon...

Page 85: ...The analog to digital conversion process can now be initialised by setting the START bit in the ADCR register from low to high and then low again Note that this bit should have been originally cleared to zero Step 7 To check when the analog to digital conversion process is complete the EOCB bit in the ADCR register can be polled The conversion process is complete when this bit goes low When this o...

Page 86: ...n power consumption A D Transfer Function As the devices contain a 12 bit A D converter respectively its full scale converted digitised value is equal to FFFH Since the full scale analog input value is equal to the VDD or VREF voltage this gives a single bit analog input value of VDD or VREF divided by 4096 1 LSB VDD or VREF 4096 The A D Converter input voltage value can be calculated using the fo...

Page 87: ...I disable ADC interrupt mov a 01H mov ACSR a select fSYS 8 as A D clock Select VDD as ADC reference voltage and turn on ADONB bit mov a FFh setup ADPCR to configure pins AN0 AN7 mov ADPCR a mov a 00h mov ADCR a enable and connect AN0 channel to A D converter start_conversion clr START high pulse on start bit to initiate conversion set START reset A D clr START start A D polling_EOC sz EOCB poll th...

Page 88: ... D clr START start A D clr ADF clear ADC interrupt request flag set EADI enable ADC interrupt set EMFI enable Multi function interrupt set EMI enable global interrupt ADC interrupt service routine ADC_ISR mov acc_stack a save ACC to user defined memory mov a STATUS mov status_stack a save STATUS to user defined memory mov a ADRL read low byte conversion result value mov adrl_buffer a save result t...

Page 89: ... communicating with external hardware device The communication is full duplex and operates as a slave master type where the devices can be either master or slave Although the SPI interface specification can control multiple slave device from a single master but this device provides only one SCS pin If the master needs to control multiple slave devices from a single master the master can use I O pi...

Page 90: ...e SIM function then the SIMEN bit in the SIMC0 register will have no effect Another two SPI configuration options determine if the CSEN and WCOL bits are to be used SPI Registers There are three internal registers which control the overall operation of the SPI interface These are the SIMD data register and two registers SIMC0 and SIMC2 Note that the SIMC1 register is only used by the I2 C interfac...

Page 91: ...n flag etc SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN R W R W R W R W R W R W R W R W POR 1 1 1 0 0 0 0 Bit 7 5 SIM2 SIM1 SIM0 SIM Operating Mode Control 000 SPI master mode SPI clock is fSYS 4 001 SPI master mode SPI clock is fSYS 16 010 SPI master mode SPI clock is fSYS 64 011 SPI master mode SPI clock is fSUB 100 SPI master mode SPI clock is Timer 0 output 2 ...

Page 92: ...0 0 0 0 0 Bit 7 6 Undefined bit This bit can be read or written by user software program Bit 5 CKPOLB Determines the base condition of the clock line 0 the SCK line will be high when the clock is inactive 1 the SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line if the bit is high then the SCK line will be low when the clock is inactive Wh...

Page 93: ...ed The TRF bit is the Transmit Receive Complete flag and is set 1 automatically when an SPI data transmission is completed but must set to 0 by the application program It can be used to generate an interrupt SPI Communication After the SPI interface is enabled by setting the SIMEN bit high then in the Master Mode when data is written to the SIMD register transmission reception will begin simultane...

Page 94: ...Rev 1 40 94 March 29 2019 HT45F23A HT45F24A TinyPowerTM Flash MCU with OPA Comparators SPI Master Mode Timing SPI Slave Mode Timing CKEG 0 SPI Slave Mode Timing CKEG 1 ...

Page 95: ...e such as sensors EEPROM memory etc Originally developed by Philips it is a two line low speed serial interface for synchronous serial data transfer The advantage of only two lines for communication relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications I2 C Master Slave Bus Conn...

Page 96: ...er will have no effect A configuration option exists to allow a clock other than the system clock to drive the I2 C interface Another configuration option determines the debounce time of the I2 C interface This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation The debounce time if selec...

Page 97: ... external Master device Bit 4 PCKEN PCK Output Pin Control 0 Disable 1 Enable Bit 3 2 PCKP1 PCKP0 Select PCK output pin frequency 00 fSYS 01 fSYS 4 10 fSYS 8 11 Timer 0 output 2 PFD0 Bit 1 SIMEN SIM Control 0 Disable 1 Enable The bit is the overall on off control for the SIM interface When the SIMEN bit is cleared to zero to disable the SIM interface the SDI SDO SCK and SCS or SDA and SCL lines wi...

Page 98: ...slave device is transmitter or receiver 0 Slave device is the receiver 1 Slave device is the transmitter Bit 3 TXAK I2 C Bus transmit acknowledge flag 0 Slave send acknowledge flag 1 Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag After the slave device receipt of 8 bits of data this bit will be transmitted to the bus on the 9th clock from the slave device The slav...

Page 99: ...he SIMD register After the data is received from the I2 C bus the device can read it from the SIMD register Any transmission or reception of data from the I2 C bus must be made via the SIMD register SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR x x x x x x x x x unknown Bit 7 0 D7 D0 SIM Data Register bit7 bit0 SIMA Register Bit 7 6 5 4 3 2 ...

Page 100: ...ering the interrupt service routine the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8 bit data transfer During a data transfer note that after the 7 bit slave address has been transmitted the following bit which is the 8th bit is the read write bit whose value will be placed in t...

Page 101: ...iving this 7 bit address data will compare it with their own 7 bit slave address If the address sent out by the master matches the internal address of the microcontroller slave device then an internal I2 C bus interrupt signal will be generated The next bit following the address which is the 8th bit defines the read write status and will be saved to the SRW bit of the SIMC1 register The slave devi...

Page 102: ...nsmitter or a receiver If the SRW flag is high the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to 1 If the SRW flag is low then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to 0 I2 C Bus Data and Acknowledge Signal The transmitted data is 8 bits wide and is transmitted afte...

Page 103: ...e When a slave address is matched the device must be placed in either the transmit mode and then write data to the SIMD register or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line I2 C Communication Timing Diagram I2 C Bus ISR Flow Chart ...

Page 104: ...master mode SPI clock is fSYS 64 011 SPI master mode SPI clock is fSUB 100 SPI master mode SPI clock is Timer 0 output 2 PFD0 101 SPI slave mode 110 I2 C slave mode 111 Unused mode These bits setup the overall operating mode of the SIM function As well as selecting if the I2 C or SPI function they are used to control the SPI Master Slave selection and the SPI Master clock frequency The SPI clock i...

Page 105: ...erate the necessary VDD 2 voltage levels for LCD 1 2 bias operation The LCDEN bit in the LCDC register is the overall master control for the LCD driver however this bit is used in conjunction with the COMnEN bits to select which I O pins are used for LCD driving Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation The following blo...

Page 106: ...EN PC6 or SCOM3 selection 0 GPIO 1 SCOM3 Bit 2 COM2EN PC5 or SCOM2 selection 0 GPIO 1 SCOM2 Bit 1 COM1EN PC4 or SCOM1 selection 0 GPIO 1 SCOM1 Bit 0 COM0EN PA0 or SCOM0 selection 0 GPIO 1 SCOM0 Note These devices provide the LCD buffer function which is controlled by LCDBUF flag to prevent the interference from LCD panel With this buffer that will provide more stable reference voltages VH0 1 VL0 1...

Page 107: ...vice LDOC Register Bit 7 6 5 4 3 2 1 0 Name VLOE REN1 VRES VSEL LDOEN R W R W R W R W R W R W POR 0 0 0 0 0 Bit 7 5 unimplemented read as 0 Bit 4 VLOE LDO output voltage control bit 0 disable 1 enable If the VLOE and LDOEN are set to 1 the LDO will output 2 4V or 3 3V to pin and disable I O function Bit 3 REN1 Bias voltage divided resistor control bit 0 disable 1 enable If the REN1is set to 1 that...

Page 108: ...0K BUF1 A D Converter VDD VRSEL A D Reference Voltage VREF VCAP SW4 VLDO Note 1 The total resistance of the divided resistors can be 500kΩ or 200kΩ selected using the ISEL bit in the LCDC register 2 The BUF1 will be switched off regardless of the VLOE bit status if the LDO is disabled 3 An external capacitor with a capacitance of 0 1μF should be connected between the VCAP pin and ground if the LDO...

Page 109: ...s read only Bit 6 0 Undefined OPA1C1 Register Bit 7 6 5 4 3 2 1 0 Name A1O2CIN A1O2N A1PSEL1 A1PSEL0 A1PS A1NS A1OEN A1EN R W R W R W R W R W R W R W R W R W POR 0 0 0 0 1 1 0 0 Bit 7 A1O2CIN OPA1 output to comparator input control bit 0 disable 1 enable The A1O2CIN bit should be set to 1 after the CNPSEL bit is set to 0 to ensure that the OPA1 output is successfully selected as the comparator inp...

Page 110: ...to 1 after the CNPSEL and A1O2CIN bits are set to 0 to ensure that the OPA2 output is successfully selected as the comparator input Bit 6 A2O2N OPA2 output to OPA2 Inverting input control bit 0 disable 1 enable This bit is only available when the A2EN bit is set to 1 If the A2EN bit is set to 0 the A2O2N bit will be cleared to 0 by hardware Bit 5 4 A2PSEL1 A2PSEL0 OPA2 Non inverting input selectio...

Page 111: ...A2N bit being set to 1 Bit 6 A1O2A2P OPA1 output to OPA2 Non inverting input control bit 0 disable 1 enable To select the OPA1 output as the OPA2 non inverting input the A2PS bit should first be set to 0 followed by the A1O2A2N bit being set to 1 Bit 5 4 unimplemented read as 0 Bit 3 PGAEN OPA2 PGA gain enable control bits 0 disable 1 enable Bit 2 0 PGA2 PGA1 PGA0 OPA2 Gain control bits 000 1 001 ...

Page 112: ... be connected to the internal comparators as shown in the block diagram Each of the OPAs has its own control register with the name OPA1C0 OPA1C1 OPA2C0 OPA2C1 and OPA2C2 which are used to control the enable disable function the calibration procedure and the programmable gain function of OPA2 OPA1 Switch Control The following diagram and table illustrate the OPA1 switch control setting and the cor...

Page 113: ...0 0 Off On Off S9C On Input A1N VM 0 1 11 0 Off On Off S8C On Input A1N VL1 1 1 00 1 On On On Off Input A1N A1P connect A1N A1E 1 0 00 1 On Off On Off Input A1P OPA1 as unit gain buffer 0 1 01 0 Off On Off S10C On Input A1N VH1 0 1 10 0 Off On Off S9C On Input A1N VM 0 1 11 0 Off On Off S8C On Input A1N VL1 Note The A1O2N bit is only available when the OPA1 is enabled by setting the A1EN bit high ...

Page 114: ...For example The PGAEN 1 will force S6D S7D to close and the PGAEN 0 will force S6D S7D to open When the A2EN 0 these switches S6D S7D and S9D are opened by hardware then the related I O pins can be used as the other functions OPA1 A1O2A2P A1O2A2N S11D S8D S12D S13D S14D VH1 VM VL1 A2O2N S9D 560K S7D S6D 10K A2NS S5D A2PS S4D A2P A2N A2O2CIN S10D CMP1 CMP2 A2E A2X A2OEN OPA2 Switch priority S4D S11...

Page 115: ...ff Off Input A2N A2P 1 0 00 0 0 0 1 On Off Off Off On Off Off Input A2P OPA2 as buffer 0 0 01 0 0 0 1 Off Off Off Off Off Off S12D On Input VH1 OPA2 as buffer 0 0 10 0 0 0 1 Off Off Off Off Off Off S13D On Input VM OPA2 as buffer 0 0 11 0 0 0 1 Off Off Off Off Off Off S14D On Input VL1 OPA2 as buffer OPA2 I O status description The following table illustrates the OPA2 I O settings A2EN PGAEN A2NS ...

Page 116: ...n interrupt trigger with edge control function Additional comparator functions include the power down control Comparator Registers The internal dual comparators are fully under the control of internal registers CMP1C0 CMP1C1 CMP2C0 and CMP2C1 These registers control enable disable function input path selection interrupt edge control and input offset voltage calibration function CMP1C0 Register Bit...

Page 117: ... or disable control bit 0 disable 1 enable CMP2C0 Register Bit 7 6 5 4 3 2 1 0 Name CMP2X C2OFM C2RS C2OF4 C2OF3 C2OF2 C2OF1 C2OF0 R W R R W R W R W R W R W R W R W POR 0 0 0 1 0 0 0 0 Bit 7 CMP2X comparator output positive logic This bit is read only Bit 6 C2OFM Comparator mode or input offset voltage cancellation mode 0 comparator mode 1 input offset voltage cancellation mode When the C2OFM 1 co...

Page 118: ... enable or disable control bit 0 disable 1 enable Comparator Functions These two comparators can operate together with the OPAs or standalone as shown in the main functional blocks of the OPAs and Comparators Each of the internal comparators in the devices allows for a common mode adjustment method of its input offset voltage The calibration steps are as following 1 Set C1OFM 1 to setup the offset...

Page 119: ...back to its original value When the CMP2 in calibration mode i e C2OFM 1 then the SW1 SW2 will be forced to close The CNPSEL and C2PSEL bits will be set 1 by hardware and these two bits will be read out as 1 After the offset voltage calibration the CNPSEL and C2PSEL will be back to its original value If the CNPSEL 1 the A1O2CIN and A2O2CIN will be forced to 0 i e If the SW1 is closed and that will...

Page 120: ... OPA1 or OPA2 output C2P is from VL0 input PA2 is I O 1 0 0 1 CNP is from OPA1 or OPA2 output C2P is from PC6 input PA2 is I O 1 0 1 0 CNP is from PA0 input C2P is from VL0 input PA2 is I O 1 0 1 1 CNP is from PA0 input C2P is from PC6 input PA2 is I O 1 1 0 0 CNP is from OPA1 or OPA2 output C2P is from VL0 input PA2 is comparator output 1 1 0 1 CNP is from OPA1 or OPA2 output C2P is from PC6 inpu...

Page 121: ... their corresponding request flag if their appropriate interrupt enable bit is set When this happens the Program Counter which stores the address of the next instruction to be executed will be transferred onto the stack The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector The microcontroller will then fetch its next instruction fr...

Page 122: ...nterrupt vector which is 18H Each of these interrupts has their own individual interrupt flag but also share the same MFF interrupt flag The MFF flag will be cleared by hardware once the Multi function interrupt is serviced however the individual interrupts that have triggered the Multi function interrupt need to be cleared by the application program INTC0 Register Bit 7 6 5 4 3 2 1 0 Name T0F EIF...

Page 123: ...read as 0 Bit 6 MFF Multi function interrupt request flag 0 inactive 1 active Bit 5 SIMF SIM interrupt request flag 0 inactive 1 active Bit 4 TIF Timer Event counter 1 interrupt request flag 0 inactive 1 active Bit 3 unimplemented read as 0 Bit 2 EMFI Multi function interrupt enable 0 disable 1 enable Bit 1 ESIM SIM interrupt enable 0 disable 1 enable Bit 0 ET1I Timer Event counter 1 interrupt ena...

Page 124: ...pt request flag 0 inactive 1 active Bit 6 TB1F Time Base 1 interrupt request flag 0 inactive 1 active Bit 5 TB0F Time Base 0 interrupt request flag 0 inactive 1 active Bit 4 ADF A D converter interrupt request flag 0 inactive 1 active Bit 3 EPI External peripheral interrupt enable 0 disable 1 enable Bit 2 TB1E Time Base 1 enable 0 disable 1 enable Bit 1 TB0E Time Base 0 enable 0 disable 1 enable B...

Page 125: ...first be set Additionally the correct interrupt edge type must be selected using the INTEDGE register to enable the external interrupt function and to choose the trigger edge type As the external interrupt pins are pin shared with I O pins they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set The pin must ...

Page 126: ...parator E2F EEPROM LVDF LVD Timer Event Counter1 Interrupt Structure The external interrupt pins are connected to an internal filter to reduce the possibility of unwanted external interrupts due to adverse noise or spikes on the external interrupt input signal As this internal filter circuit will consume a limited amount of power a configuration option is provided to switch off the filter function...

Page 127: ...is configured as a peripheral interrupt pin via a configuration option When the interrupt is enabled the stack is not full and a negative transition type appears on the external peripheral interrupt pin a subroutine call to the Multi function interrupt vector at location18H will take place When the external peripheral interrupt is serviced the EMI bit will be cleared to disable other interrupts ho...

Page 128: ... an External Peripheral Interrupt a Comparator output interrupt an EEPROM Write or Read cycle ends interrupt or a LVD interrupt is generated When the interrupt is enabled and the stack is not full and either one of the interrupts contained within the Multi function interrupt occurs a subroutine call to the Multi function interrupt vector at location 018H will take place When the interrupt is servi...

Page 129: ... interrupts The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods Their clock sources originate from the internal clock source fTB This fTB input clock passes through a divider the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges The clock source that generates ...

Page 130: ...only the Multi function interrupt request flag will be also automatically cleared As the E2F flag will not be automatically cleared it has to be cleared by the application program LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi function Interrupt An LVD Interrupt request will take place when the LVD Interrupt request flag LVDF is set which occurs when the Low Voltage...

Page 131: ...PCTL register is used to select from one of three buzzer options The first option is for both pins PA6 and PA7 to be used as normal I Os the second option is for both pins to be configured as BZ and BZ buzzer pins the third option selects only the PA6 pin to be used as a BZ buzzer pin with the PA7 pin retaining its normal I O pin function Note that the BZ pin is the inverse of the BZ pin which tog...

Page 132: ...ion as a BZ buzzer pin then the PA7 pin can be used as a normal I O pin For the PA6 pin to function as a BZ buzzer pin PA6 must be setup as an output by setting bit PAC6 of the PAC port control register to zero The PA6 data bit in the PA data register must also be set high to enable the buzzer output if set low pin PA6 will remain low In this way the PA6 bit can be used as an on off control for th...

Page 133: ...warning battery low signal to be generated The Low Voltage Detector also has the capability of generating an interrupt signal LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC Three bits in this register VLVD2 VLVD0 are used to select one of eight fixed voltages below which a low voltage condition will be detemined A low voltage condition is in...

Page 134: ...e powered down the low voltage detector will remain active if the LVDEN bit is high After enabling the Low Voltage Detector a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit Note also that as the VDD voltage may rise and fall rather slowly at the voltage nears that of VLVD there may be multiple bit LVDO transitions The Low Voltage Detector also has its...

Page 135: ...t 3 bits of this register are used for volume control and the DACEN bit is used to control the DAC function enable or not Once the DACEN bit is set to 1 this will channel the DAC output to the I O pin and disable the original I O pin shared function DAL Register Bit 7 6 5 4 3 2 1 0 Name D3 D2 D1 D0 R W R W R W R W R W POR 0 0 0 0 Bit 7 5 D3 D2 Audio output low 4 bit Bit 3 0 unimplemented read as 0...

Page 136: ...ns Oscillator Options 1 OSC type selection ERC or crystal or HIRC or EC external clock 00 HXT Filter ON 01 ERC Filter ON 10 HIRC Filter OFF 11 EC Filter OFF 2 Low speed system oscillator selection fL LXT LIRC 3 HIRC frequency selection 4MHz 910kHz 2MHz 8MHz 4 fS clock selection fSUB or fSYS 4 5 HXT mode selection 455kHz or 1M 8MHz Watchdog Options 6 WDT enable or disable 7 CLR WDT instructions 1 o...

Page 137: ...Rev 1 40 137 March 29 2019 HT45F23A HT45F24A TinyPowerTM Flash MCU with OPA Comparators Application Circuits ...

Page 138: ...one more cycle to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is involved then ...

Page 139: ... of branch instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined by the cond...

Page 140: ...Memory 1Note Z C AC OV DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data Memory 1Note Z AND A x Logical AND...

Page 141: ... None RET A x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table specific page or current page to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None Miscellaneous NOP No operation 1 None CLR m Clear Data Memory 1Note None SET m Set Data Memory 1Note None CLR WDT Clear W...

Page 142: ... Accumulator and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C AND A m Logical AND Data Memory to ACC Descripti...

Page 143: ...on The TO PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect Repetitively executing this instruction without alternately executing CLR WDT2 wi...

Page 144: ...cted by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H or m ACC 66H Affected flag s C DEC m Decrement Data Memory Description Data in the specified Data Memory is decremented by 1 Operation m m 1 Affected flag s Z DECA m Decrement Data Memory with result in ACC Description...

Page 145: ...peration m ACC Affected flag s None NOP No operation Description No operation is performed Execution continues with the next instruction Operation No operation Affected flag s None OR A m Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation The result is stored in the Accumulator Operation ACC ACC OR m Affected flag ...

Page 146: ...tate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 m 7 Affected flag s None RLC m Rotate Data Memory left through Carry Description The contents of the specified Dat...

Page 147: ...g s C SBC A m Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Accumulator Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is positive or zero the C flag will be set to 1 Operation ACC ACC m C A...

Page 148: ...not 0 the program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SIZA m Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped The result is stored in the Accumulator but the specified Data Memory contents remain unchan...

Page 149: ...Memory are interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fet...

Page 150: ...emory and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None XOR A m Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation The result is stored in the Accumulator Operation ACC ACC XOR m Affected flag s Z XORM A m Logical XOR ACC to Data Memory Description ...

Page 151: ...d at regular intervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Further Package Information include Outline Dimensions Product Tape and Reel Specifications Packing Meterials Inform...

Page 152: ...tline Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 012 0 020 C 0 390 BSC D 0 069 E 0 050 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 0 BSC B 3 9 BSC C 0 31 0 51 C 9 9 BSC D 1 75 E 1 27 BSC F 0 10 0 25 G 0 40 1 27 H 0 10 0 25 α 0 8 ...

Page 153: ...line Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 341 BSC D 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 0 BSC B 3 9 BSC C 0 20 0 30 C 8 66 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 α 0 8 ...

Page 154: ...line Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 341 BSC D 0 069 E 0 025 BSC F 0 004 0 0098 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 0 BSC B 3 9 BSC C 0 20 0 30 C 8 66 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 α 0 8 ...

Page 155: ...tline Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 390 BSC D 0 069 E 0 025 BSC F 0 004 0 0098 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 0 BSC B 3 9 BSC C 0 20 0 30 C 9 9 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 α 0 8 ...

Page 156: ...ein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holt...

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Summary of Contents for HT45F23A

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Holtek HT45F23A, Manual, Page: 115 / 156

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