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HOLT ADK-2130mPCIe, Technical Manual

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HOLT ADK-2130mPCIe Technical Manual Download Page 44

5

5

4

4

3

3

2

2

1

1

E

E

D

D

C

C

B

B

A

A

MEMS OSC 100MHz

2x .1uF close to pins

2x .1uF close to pins

4.7uF close but outside
 FPGA perimeter.

4.7uF close but outside
 FPGA perimeter.

.47uF close as possible to pins

47 and 4.7 near perimeter.

Near FPGA pin V1 for minimum distance.
10 ohm near Osc module.

3x .1uF close to pins

47 and 4.7 near perimeter.

ADC input. 10V
Max.

CH0INHIBIT0

CHANNEL 0 BPOS

CH02

CHANNEL 0 BNEG

CH03

CHANNEL 0 ANEG

CH01

CHANNEL 0 APOS

CH00

CH04

CH0INHIBIT0

CH05

CH0BCENA0

CH06

CH0BCTRIG0

CHANNEL 0 APOS CH00
CHANNEL 0 ANEG CH01

MCLK100M

DEV00
DEV01
DEV02
DEV03

RT1ENA0

DEV05

RT2ENA0

DEV04

RT1MC80

DEV07

MCLK50

DEV06

RT2MC80

DEV09

TTCLK

DEV08

MTTCLK

DEV011

MTPKTRDY0

DEV010

MTRUN0

READY0

DEV012

ACTIVE0

DEV013

nIRQ0

DEV014

nMR0

DEV015

MCLK100M

MCLK50

CHANNEL 1 APOS

CH10

CHANNEL 1 ANEG

CH11

CHANNEL 1 BNEG

CH13

CHANNEL 1 BPOS

CH12

CH14

CH1INHIBIT1

CH16

CH1BCTRIG1

CH15

CH1BCENA1

CHANNEL 0 BPOS CH02
CHANNEL 0 BNEG CH03

CHANNEL 1 APOS CH10
CHANNEL 1 ANEG CH11

CHANNEL 1 BPOS CH12
CHANNEL  1BNEG CH13

RT1ENA1

DEV13

DEV12

DEV11

DEV10

RT2MC81

DEV16

MCLK50

DEV17

RT1MC81

DEV14

RT2ENA1

DEV15

MTRUN1

DEV110

MTPKTRDY1 DEV111

MTTCLK

DEV18

TTCLK

DEV19

nIRQ1

DEV114

ACTIVE1

DEV113

READY1

DEV112

nMR1

DEV115

RT1ENA0
RT1ENA1
RT2ENA0
RT2ENA1

nMR0
nMR1

nIRQ0
nIRQ1

READY1

led0

MTRUN0

led3

led2

led1

CH0BCENA0

CH1BCTRIG1

CH0BCTRIG0

MTRUN1

CH1BCENA1

TEST1

MTTCLK

TTCLK

RT1MC81

TEST0

RT2MC80

READY0

ACTIVE1

ACTIVE0
RT1MC80
RT2MC81

MTPKTRDY0

MTPKTRDY1

TEST0

DEV016

TEST1

DEV116

led0

led1

led2

led3

SPAREINPUT

GPIO

GND

CH0BCENA0_IN

SPAREINPUT

CH1INHIBIT1
CH1BCENA1_IN
CH1BCTRIG1_IN

CH0BCTRIG0_IN

3V3aux

GND

GPIO

CH0[10:0]

DEV0[16:0]

CH1[10:0]

DEV1[16:0]

ADCINP

ADCINN

MGTAVTT1V2

VCCAUX_1V8

VCCINT_1V

VCCO3V3

VCCO3V3

VCCO3V3

MGTAVCC1V

VCCO3V3aux0

VCCO3V3aux1

VCCINT_1V

VCCAUX_1V8

VCCO3V3

MGTAVCC1V

MGTAVTT1V2

VCCO3V3aux0

VCCO3V3aux1

VCCINT_1V

VCCAUX_1V8

VCCO3V3

MGTAVCC1V

MGTAVTT1V2

3V3aux

GND

Title

Size

Document Number

R e v

Date:

Sheet

o f

<Doc>

A

Holt PCIe-Mini dual MIL-STD 1553

B

5

5

Thursday, January 16, 2020

Title

Size

Document Number

R e v

Date:

Sheet

o f

<Doc>

A

Holt PCIe-Mini dual MIL-STD 1553

B

5

5

Thursday, January 16, 2020

Title

Size

Document Number

R e v

Date:

Sheet

o f

<Doc>

A

Holt PCIe-Mini dual MIL-STD 1553

B

5

5

Thursday, January 16, 2020

2x1.6mm

100MHZ OSC

U13

OE

1

OUT

3

VDD

4

GN

D

2

R34 10K

R35 10K

R32 10K

D4

TPD4E02B04DQAR

1

9

2

3

4

7

8

10

6

5

U10A

74LVC2G14

1

6

C63

0.47uF

C67
.1uF

R41

470

U12B

74LVC2G14

3

4

C58

4.7uF

C62

0.47uF

R42

470

Mt1

Mt Plated

R40

0

R37
9.1K

C69

0.47uF

R43

470

XC7A12T-2CPG238

U2D

IO_0_34

G3

IO_L1P_T0_34

G2

IO_L1N_T0_34

G1

IO_L2P_T0_34

H3

IO_L2N_T0_34

H2

IO_L3P_T0_DQS_34

H1

IO_L3N_T0_DQS_34

J1

IO_L4P_T0_34

K2

IO_L4N_T0_34

K1

IO_L5P_T0_34

J3

IO_L5N_T0_34

K3

IO_L6P_T0_34

L3

IO_L6N_T0_VREF_34

L2

IO_L7P_T1_34

L1

IO_L7N_T1_34

M1

IO_L8P_T1_34

N2

IO_L8N_T1_34

P2

IO_L9P_T1_DQS_34

N1

IO_L9N_T1_DQS_34

P1

IO_L10P_T1_34

M3

IO_L10N_T1_34

N3

IO_L11P_T1_SRCC_34

R1

IO_L11N_T1_SRCC_34

T1

IO_L12P_T1_MRCC_34

P3

IO_L12N_T1_MRCC_34

R3

IO_L13P_T2_MRCC_34

T3

IO_L13N_T2_MRCC_34

T2

IO_L14P_T2_SRCC_34

U1

IO_L14N_T2_SRCC_34

V1

IO_L15P_T2_DQS_34

U3

IO_L15N_T2_DQS_34

U2

IO_L16P_T2_34

U4

IO_L16N_T2_34

V3

IO_L17P_T2_34

V4

IO_L17N_T2_34

W4

IO_L18P_T2_34

W3

IO_L18N_T2_34

W2

IO_L19P_T3_34

U6

IO_L19N_T3_VREF_34

U5

IO_L20P_T3_34

W6

IO_L20N_T3_34

W5

IO_L21P_T3_DQS_34

U7

IO_L21N_T3_DQS_34

V6

IO_L22P_T3_34

U9

IO_L22N_T3_34

U8

IO_L23P_T3_34

W9

IO_L23N_T3_34

W8

IO_L24P_T3_34

V7

IO_L24N_T3_34

W7

IO_25_34

V9

VCCO_34

J7

VCCO_34

K7

VCCO_34

L7

VCCO_34

M7

VCCO_34

M8

VCCO_34

N7

VCCO_34

N8

R44

470

U9B

74LVC2G14

3

4

U11

74LVC1G14 SC70

2

4

R29 10K

C65
.1uF

R38
1K

+

C57

47uF

TP12

C55

4.7uF

R36 10K

C60
.1uF

U10B

74LVC2G14

3

4

+

C53

47uF

R30 10K

C61

4.7uF

R33 10K

C66
.1uF

C50

.1uF

C52

.47uF

Mt2

Mt Plated

R28

330

D6

LED

C68

4.7uF

+

C56

47uF

D7

LED

C49

.1uF

XC7A12T-2CPG238

U2F

GND

A1

GND

A3

GND

A5

GND

A7

GND

A9

GND

A19

GND

B3

GND

B5

GND

B7

GND

B9

GND

B14

GND

C2

GND

C3

GND

C4

GND

C6

GND

C10

GND

C19

GND

D3

GND

E3

GND

F1

GND

F2

GND

F3

GND

F18

GND

G8

GND

G11

GND

H7

GND

H8

GND

H11

GND

H12

GND

J2

GND

J8

GND

J9

GND

J11

GND

J12

GND

J18

GND

K8

GND

L8

GND

L9

GND

L11

GND

M2

GND

M9

GND

M18

GND

N9

GND

N12

GND

R2

GND

R18

GND

V2

GND

V5

GND

V8

GND

V12

GND

V15

GND

V18

GND

W1

GND

W19

VCCBRAM

M11

VCCBRAM

N11

VCCINT

G10

VCCINT

H10

VCCINT

J10

VCCINT

L10

VCCINT

M10

VCCINT

N10

VCCAUX

H13

VCCAUX

J13

MGTAVCC

C1

MGTAVCC

E1

MGTAVCC

G9

MGTAVCC

H9

MGTAVTT

B1

MGTAVTT

C5

MGTAVTT

E2

MGTAVTT

G7

D5

TPD4E02B04DQAR

1

9

2

3

4

7

8

10

6

5

D8

LED

U12A

74LVC2G14

1

6

U9A

74LVC2G14

1

6

R31 10K

C54

.1uF

J4

Primary 20 pin conn.

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20

C64

0.47uF

TP11

D9

LED

+

C51

47uF

C59

0.47uF

R39

10

Summary of Contents for ADK-2130mPCIe

Page 1: ...AN 2130mPCIe_New 01 20 ADK 2130mPCIe Technical Manual Jan 16 2020...

Page 2: ...This page intentionally blank...

Page 3: ...Holt Integrated Circuits 3 REVISION HISTORY Revision Date Description of Change AN 2130mPCIe Rev New 1 16 20 Initial Release...

Page 4: ...on to the card Application Development Kit ADK contents and how to run the demonstration software using the Holt bootable Flash Drive Use the instructions in this guide to install the Holt software an...

Page 5: ...TC3545 1 spare 3 3VMOSFET switch 100MHz MEMS OSC Quad SPI FLASH JTAG 8 pin to FPGA 3 3aux VCCINT 1V MGTAVCC1V VCC1 8V JTAG VCCO 3V3 52 pin PCIe conn Xilinx ARTIX 7 XC7A127 2CPG238I 10 x 10 HI 2130 36...

Page 6: ...h which present a low to the HI 2130 devices which enables 1553 bus transmissions by default Table 8 is a list of the signals and descriptions on the inter connect ribbon J4 connector For board compon...

Page 7: ...has not tried any other Linux version as of this date Windows support is planned in the future https ubuntu com download 5 Power up the PC Shortly after powering up the computer the green PCIe Link L...

Page 8: ...s complete optionally launch eclipse to see it working then exit the program It s possible to create a program short cut from a terminal window where eclipse is installed then drag the link to the des...

Page 9: ...clipse Project Explorer PE window isn t shown type in Project Explorer into the Quick Access window located on the top right corner of the screen and select it from the list of items shown The three p...

Page 10: ...ble kernel module pcie_lkm ko This module must be loaded into the Linux OS before executing the Demo project or an error will be produced This module provides support for writing and reading HI 2130 d...

Page 11: ...t is modified and rebuilt the exiting kernel module must be unloaded before the new one is reloaded sudo sh unload_pcie_load sudo sh load_pcie_load These script commands were embedded in the run scrip...

Page 12: ...rs asking to select either C C Controller Application or Local C C Application Select Local C C Application c The debugger should present main c in a window with the first line of code highlighted in...

Page 13: ...Holt Integrated Circuits 13...

Page 14: ...reparations Before running the Demo connect the ribbon cable between the PCIe card and the Break Out board Carefully insert the small ribbon cable to the Mini PCIe Card J4 connector and the other end...

Page 15: ...chan 0 HIGH READY asserted Setting nMR chan 1 LOW Setting nMR chan 1 HIGH READY asserted Number of Devices found 2 Initial default RT addresses DEV0 RT1 3 DEV0 RT2 1 DEV1 RT1 3 DEV1 RT1 Optionally use...

Page 16: ...This is useful to see all the system registers at a glance Using sub commands allow moving up and down in memory space This is more useful to see large areas of memory such as RT control blocks BC me...

Page 17: ...2626 2727 2828 2929 3030 3131 3232 Dev0 MSG 0003 TIME 00042720us BUS A TYPE0 BC to RT CMD1 1BC0 03 R 30 00 DATA 0101 0202 0303 0404 0505 0606 0707 0808 0909 1010 1111 1212 1313 1414 1515 1616 1717 18...

Page 18: ...303 0404 0505 0606 0707 0808 0909 1010 1111 1212 1313 1414 1515 1616 1717 1818 1919 2020 2121 2222 2323 2424 2525 2626 2727 2828 2929 3030 3131 3232 STA1 1800 Dev0 MSG 0010 TIME 00047602us BUS B TYPE1...

Page 19: ...in on bus B into the message sequence while running the BC Async demo command a This will only occur once Dev0 MSG 1694 TIME 00070698us BUS B TYPE0 BC to RT CMD1 0822 01 R 01 02 DATA DEAD BEEF STA1 08...

Page 20: ...v1 b c k RTMT Demo t Traffic Enabled B C K RTMT Demo a A this will be seen much later inter mixed in the messages below With a 2F card a mixed of messages from Dev0 and Dev1 are displayed Dev0 MSG 028...

Page 21: ...he default is Demo mode Command f reads and displays the states of the FPGA control signals going to both Dev0 and Dev1 The signals are listed in Table 1 in the next section See the next section for a...

Page 22: ...o Mode vs User Mode For ease of software demonstration a Demo Mode is selected when location INPUT_CONTROL 0x800D is set low and a User Mode is selected when it is high The power up default is Demo Mo...

Page 23: ...t High to Enable RT1 RT2ENA FPGA Device Enables RT2 0x800B Read Write Set High to Enable RT2 TXINHA TXINHB J4 Connector Inhibits bus 0x800C Read only Hard wired to J4 INPUT_CONTROL FPGA Set Demo mode...

Page 24: ...re 3 Board References should be pulled high which will drive M2 high For normal use these connections don t need to be altered by the user only if the user wants to customize the Verilog design and wa...

Page 25: ...oth devices Unique chip select lines nCE0 and nCE1 are used to select between them Table 3 HI 2130 Common Interface Signals to FPGA HI 2130 FPGA BANK PRIMARY CONNECTOR COMMENTS Address pins A15 A0 14...

Page 26: ...FPGA RT2MC80 34 RT2MC8 output input to FPGA CH0BCENAB0 BCENA 34 YES Default enabled by pull up resistor Can be set low by the connector or the FPGA can override it CH0BCTRIG BCTRIG 34 YES Normally lo...

Page 27: ...ES Default enabled by pull up resistor Can be set low by the connector or the FPGA can override it CH1BCTRIG BCTRIG 34 YES Normally low Can be pulsed at connector or the FPGA can override it MTRUN1 34...

Page 28: ...3V3 supply to meet Xilinx power sequencing recommendations to power the SPI Flash MEMS oscillator and the FPGA bank 14 15 and 34 rails Table 6 Power Supply Power Supply Voltage Schematic Name Functio...

Page 29: ...y Cycle ICC Amps 3 3V 69 ohm load U7 2130 C Temp Board flat open air U8 2130 C Board flat open air 0 100 1 07 70 56 0 1 100 1 86 82 78 0 1 100 1 86 50 with fan 45 with fan 0 1 100 1 78 81 78 0 1 50 1...

Page 30: ...hassis GND Mounting screw no other connection 10 CHANNEL 1 BPOS MIL STD 1553 CH1 B 11 CHANNEL 1 BNEG MIL STD 1553 CH1 B 12 Chassis GND Mounting screw no other connection 13 CH0INHBIT0 Channel 0 Transm...

Page 31: ...e design ACTIVE asserts high during any BC RT or SMT command and serves as a good starting point to check when debugging changes to the software or FPGA design See board references for test point boar...

Page 32: ...Holt Integrated Circuits 32 Figure 3 Board References...

Page 33: ...summarized the steps necessary to install the Holt Mini PCIe Eclipse project and import the project into Eclipse to allow building the projects and rerunning them See technical guide AN MPCIeVivado T...

Page 34: ...X F380J476MMAAXEH3 13 1 Res 100 1 1 20W 0201 SMD R7 P122654CT ND Panasonic ERJ 1GNF1000C 14 1 Res 226K 1 1 20W 0201 SMD R2 P122842CT ND Panasonic ERJ 1GNF2263C 15 1 Res 255K 1 1 20W 0201 SMD R5 P12287...

Page 35: ...96 43875 1 ND TI TPD4E02B04DQAR 39 1 IC Reg Linear 1V 150mA SOT23 5 U3 497 6871 1 ND ST LD39015M10R 40 1 IC Reg Linear 1 2V 150mA SOT23 5 U4 497 6872 1 ND ST LD39015M12R 41 2 IC Inverter 1CH 1 INP SC7...

Page 36: ...e FFC 20 Pos 0 5mm 5 Long J2B WM11409 ND Molex 0152660213 4 1 24 Inch Triax Plug Cable CH0 AB None MilesTek CA 2014 48 5 1 Aluminum Block 0 75 x2 5 x0 25 Tie Block None OnlineMetals 1142 6 3 Hex Nut 3...

Page 37: ...X F380J476MMAAXEH3 13 1 Res 100 1 1 20W 0201 SMD R7 P122654CT ND Panasonic ERJ 1GNF1000C 14 1 Res 226K 1 1 20W 0201 SMD R2 P122842CT ND Panasonic ERJ 1GNF2263C 15 1 Res 255K 1 1 20W 0201 SMD R5 P12287...

Page 38: ...6 43875 1 ND TI TPD4E02B04DQAR 39 1 IC Reg Linear 1V 150mA SOT23 5 U3 497 6871 1 ND ST LD39015M10R 40 1 IC Reg Linear 1 2V 150mA SOT23 5 U4 497 6872 1 ND ST LD39015M12R 41 2 IC Inverter 1CH 1 INP SC70...

Page 39: ...FC 20 Pos 0 5mm 5 Long J2B WM11409 ND Molex 0152660213 4 2 24 Inch Triax Plug Cable CH0 AB CH1 AB None MilesTek CA 2014 48 5 1 Aluminum Block 0 75 x2 5 x0 25 Tie Block None OnlineMetals 1142 6 3 Hex N...

Page 40: ...3 B 1 5 Thursday January 16 2020 Title Size Document Number Rev Date Sheet o f Doc A Holt PCIe Mini dual MIL STD 1553 B 1 5 Thursday January 16 2020 C71 0 22uF C16 1uF C9 10pF C1 10uF REFCLK REFCLK PE...

Page 41: ...1_MRCC_AD5P_15 C15 IO_L12N_T1_MRCC_AD5N_15 B15 IO_L13P_T2_MRCC_15 C16 IO_L13N_T2_MRCC_15 B17 IO_L14P_T2_SRCC_15 B18 IO_L14N_T2_SRCC_15 A18 IO_L19N_T3_A21_VREF_15 C17 VCCO_15 B19 VCCO_15 C14 VCCO_15 C1...

Page 42: ...MIL STD 1553 B 3 5 Monday September 30 2019 Title Size Document Number Rev Date Sheet o f Doc A Holt PCIe Mini dual MIL STD 1553 B 3 5 Monday September 30 2019 Title Size Document Number Rev Date Shee...

Page 43: ...MIL STD 1553 B 4 5 Monday September 30 2019 Title Size Document Number Rev Date Sheet o f Doc A Holt PCIe Mini dual MIL STD 1553 B 4 5 Monday September 30 2019 Title Size Document Number Rev Date Shee...

Page 44: ...STD 1553 B 5 5 Thursday January 16 2020 2x1 6mm 100MHZ OSC U13 OE 1 OUT 3 VDD 4 GND 2 R34 10K R35 10K R32 10K D4 TPD4E02B04DQAR 1 9 2 3 4 7 8 10 6 5 U10A 74LVC2G14 1 6 C63 0 47uF C67 1uF R41 470 U12B...

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